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US4727043A
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US
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Method of manufacturing a non-volatile memory
Assignee: Fujitsu Ltd
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Filing: 1985-10-29
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Granted: 1988-02-23
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Expires: 2005-10-29
Abstract
Abstract An improved electrically alterable read-only memory (EAROM) is offered by the method of the invention, the memory device comprising a floating gate type field effect transistor in which a part of the floating gate and a part of the drain region formed in a silicon substrate overlap. According to the method, impurity atoms are ion implanted into a part of a region where the drain region is to be formed through an insulation layer of silicon dioxide on the region. Thereafter, the insulation layer through which ion implantation was carried out is removed and a fresh insulation layer of silicon dioxide is formed where the old insulation layer was removed. By this method, a good, thin insulation film is fabricated. By virtue of the fresh insulation layer devoid of trap centers which trap electric charges, the insulation layer is free from defects that interrupt flow of electrons required for writing or erasing of information.
Inventors
- 👤 Takashi Matsumoto
- 👤 Motoo Nakano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:58
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683; H10P30/21; H10P30/212
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
140 words
A method of manufacturing a non-volatile memory device having a part of a floating gate overlapping a part of a drain region formed in a semiconductor substrate, said method comprising the steps of: (a) forming a first insulation layer on the semiconductor substrate; (b) introducing impurity atoms into a part of the semiconductor substrate corresponding to the drain region, through the first insulation layer formed on the semiconductor substrate; (c) removing a portion of the first insulation layer overlapping the drain region on which the floating gate is to be formed, after the impurity atoms have been introduced into the semiconductor substrate, exposing a portion of the semiconductor substrate; (d) forming a second insulation layer on the exposed portion of the semiconductor substrate; and (e) forming the floating gate over the first insulation layer and on the second insulation layer.
Claim 2
Independent Claim
140 words
A method of manufacturing a non-volatile memory device having a part of a floating gate overlapping a part of a drain region formed in a semiconductor substrate, said method comprising the steps of: (a) forming a first insulation layer on the semiconductor substrate; (b) introducing impurity atoms into a part of the semiconductor substrate corresponding to the drain region, through the first insulation layer formed on the semiconductor substrate; (c) removing a portion of the first insulation layer overlapping the drain region on which the floating gate is to be formed, after the impurity atoms have been introduced into the semiconductor substrate, exposing a portion of the semiconductor substrate; (d) forming a second insulation layer on the exposed portion of the semiconductor substrate; and (e) forming the floating gate over the first insulation layer and on the second insulation layer.
Claim 3
Independent Claim
203 words
A method of manufacturing a non-volatile memory device having a floating gate formed overlapping a portion of a drain formed in a semiconductor substrate of a first conductivity type, said method comprising the steps of: (a) forming a first insulation layer on the semiconductor substrate; (b) introducing ions, having a second conductivity type opposite the first conductivity type, through the first insulation layer and into a selected area of the semiconductor substrate; (c) removing a portion of the first insulation layer overlapping the selected area of the semiconductor substrate on which the floating gate is to be formed after the ions have been introduced into the semiconductor substrate; (d) forming a second insulation layer on the selected area of the semiconductor substrate; (e) forming the floating gate overlapping a portion of the selected area of the semiconductor substrate; (f) forming a third insulation layer on the floating gate; (g) forming a control gate on the third insulation layer overlapping the floating gate; and (h) forming a source region and the drain region adjacent to the selected area of the semiconductor substrate and separated by the selected area of the semiconductor substrate by introducing ions having the second conductivity type into the semiconductor substrate.
Claim 4
Independent Claim
203 words
A method of manufacturing a non-volatile memory device having a floating gate formed overlapping a portion of a drain formed in a semiconductor substrate of a first conductivity type, said method comprising the steps of: (a) forming a first insulation layer on the semiconductor substrate; (b) introducing ions, having a second conductivity type opposite the first conductivity type, through the first insulation layer and into a selected area of the semiconductor substrate; (c) removing a portion of the first insulation layer overlapping the selected area of the semiconductor substrate on which the floating gate is to be formed after the ions have been introduced into the semiconductor substrate; (d) forming a second insulation layer on the selected area of the semiconductor substrate; (e) forming the floating gate overlapping a portion of the selected area of the semiconductor substrate; (f) forming a third insulation layer on the floating gate; (g) forming a control gate on the third insulation layer overlapping the floating gate; and (h) forming a source region and the drain region adjacent to the selected area of the semiconductor substrate and separated by the selected area of the semiconductor substrate by introducing ions having the second conductivity type into the semiconductor substrate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-02-22 | 1991-08-24 | 1992-02-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-02-22 | 1995-08-24 | 1996-02-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-02-22 | 1999-08-24 | 2000-02-23 | $7700.00 | Window Closed / Lapsed |