US4725915A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit
Assignee: Toshiba Corp
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Filing: 1985-03-29
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Granted: 1988-02-16
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Expires: 2005-03-29
Abstract
Abstract A semiconductor integrated circuit includes a MOS transistor, and a transistor circuit in which one end of a current path is connected to a drain of this MOS transistor and which has an avalanche breakdown voltage lower than a breakdown voltage of the MOS transistor.
Inventors
- 👤 Hiroshi Jwahashi
- 👤 Masamichi Asano
- 👤 Hiroshi Harada
- 👤 Shinichi Tanaka
- 👤 Hideki Sumihara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 23:16
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; H10D84/00; H10D84/80; H10D84/82; H10D84/83
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
173 words
A semiconductor integrated circuit comprising: first and second potential terminals; a first MOS transistor coupled between said first and second potential terminals; a gate-controlled diode having a gate, being connected to a drain of said first MOS transistor, and having a breakdown voltage controlled by a gate voltage applied to said gate; and a depletion type MOS transistor coupled to a mode between the gate of said gate-controlled diode and the drain of said first MOS transistor, wherein said gate-controlled diode is constituted by a substrate of one conductivity type; a first semiconductor region of an opposite conductivity type formed in the surface area of said substrate; and gate insulation layer formed on the substrate, with part of said gate insulation layer formed on a portion of said first semiconductor region; a gate electrode formed on said gate insulation layer; and a second semiconductor region of the opposite conductivity type formed in the surface area of said substrate, at a location apart from said gate insulation layer, to face said first semiconduction region.
Claim 2
Dependent Claim
173 words
A semiconductor integrated circuit comprising: first and second potential terminals; a first MOS transistor coupled between said first and second potential terminals; a gate-controlled diode having a gate, being connected to a drain of said first MOS transistor, and having a breakdown voltage controlled by a gate voltage applied to said gate; and a depletion type MOS transistor coupled to a mode between the gate of said gate-controlled diode and the drain of said first MOS transistor, wherein said gate-controlled diode is constituted by a substrate of one conductivity type; a first semiconductor region of an opposite conductivity type formed in the surface area of said substrate; and gate insulation layer formed on the substrate, with part of said gate insulation layer formed on a portion of said first semiconductor region; a gate electrode formed on said gate insulation layer; and a second semiconductor region of the opposite conductivity type formed in the surface area of said substrate, at a location apart from said gate insulation layer, to face said first semiconduction region.
Claim 3
Dependent Claim
24 words
A semiconductor integrated circuit according to claim 1, further including capacitive means coupled between said depletion type MOS transistor and said second potential terminal.
Claim 4
Dependent Claim
93 words
A semiconductor integrated circuit according to claim 1, wherein said first MOS transistor comprises: a substrate of one conductivity type; drain and source regions of an opposite conductivity type formed in the surface area of said substrate, said drain region including a first region and a second region having an impurity concentration lower than that of said first region; a gate insulation film formed on the partial area of said substrate between said source region and said second region of said drain region; and a gate electrode formed on said gate insulation film.
Claim 5
Dependent Claim
44 words
A semiconductor integrated circuit according to claim 1, further including a second depletion type MOS transistor connected to provide a current path between said first depletion type MOS transistor and a power source terminal and having a gate connected to said second potential terminal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-02-15 | 1991-08-17 | 1992-02-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-02-15 | 1995-08-17 | 1996-02-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-02-15 | 1999-08-17 | 2000-02-16 | $7700.00 | Window Closed / Lapsed |