Patent US4725878A successfully refreshed from Google Patents.
US4725878A
Expired / Lapsed
US
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Semiconductor device
Assignee: Fujitsu Ltd
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Filing: 1986-03-27
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Granted: 1988-02-16
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Expires: 2006-03-27
Abstract
Abstract A semiconductor device provided with signal lines which connect a chip, provided at a top portion of a package, with external terminals provided at a bottom portion of the package. The signal lines have portions formed along side surfaces of the package. Ground surfaces are formed at predetermined distances on two sides of the high-speed signal lines. A coplanar waveguide is formed by the high-speed signal lines and the ground surfaces, so the impedance of vertical portions of the high-speed signal lines is matched to the circuits connected thereto.
Inventors
- 👤 Akira Miyauchi
- 👤 Hiroshi Nishimoto
- 👤 Tadashi Okiyama
- 👤 Hiroo Kitasagami
- 👤 Masahiro Sugimoto
- 👤 Haruo Tamada
- 👤 Shinji Emori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:51
CPC Classifications
H; H10; H10W; H10W44/00; H10W44/20; H05; H05K; H05K1/00; H05K1/02; H05K1/0213; H05K1/0237; H05K1/0243; H10W70/00; H10W70/60; H10W70/67; H10W70/68; H10W70/685; H10W72/00; H10W72/50; H10W76/00; H10W76/10; H10W76/12; H10W76/15; H10W76/157; H05K1/0216; H05K1/0218; H05K1/0219; H05K1/18; H05K1/182; H05K1/184; H05K2201/00; H05K2201/09; H05K2201/09209; H05K2201/09218; H05K2201/09236; H05K2201/10; H05K2201/10227; H05K2201/10409; H05K2201/10613; H05K2201/10621; H05K2201/10689; H05K2201/10954; H05K2201/10969; H05K3/00; H05K3/30; H05K3/32; H05K3/325; H05K3/34; H05K3/341; H05K3/3421; H10W44/203; H10W44/216; H10W70/62; H10W70/65; H10W70/654; H10W70/655; H10W70/682; H10W72/071; H10W72/075; H10W72/07551; H10W72/07554; H10W72/541; H10W72/5449; H10W72/547; H10W90/00; H10W90/701; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
121 words
A semiconductor device having an upper and lower portion and side surfaces, comprising: a chip provided at the upper portion of said device; a plurality of external terminals provided at the lower portion of said device; a plurality of a first set of signal lines for coupling said external terminals to said chip, each of said signal lines being provided along the side surfaces of said device; and a plurality of grounding surfaces provided at a predetermined distance from each side of said first set of signal lines provided on the side surfaces, a coplanar waveguide being formed by set of signal lines on the side surfaces and said ground surfaces matching the impedance of said first type of signal lines.
Claim 2
Dependent Claim
121 words
A semiconductor device having an upper and lower portion and side surfaces, comprising: a chip provided at the upper portion of said device; a plurality of external terminals provided at the lower portion of said device; a plurality of a first set of signal lines for coupling said external terminals to said chip, each of said signal lines being provided along the side surfaces of said device; and a plurality of grounding surfaces provided at a predetermined distance from each side of said first set of signal lines provided on the side surfaces, a coplanar waveguide being formed by set of signal lines on the side surfaces and said ground surfaces matching the impedance of said first type of signal lines.
Claim 3
Dependent Claim
30 words
A semiconductor device according to claim 1, further comprising: grounding surfaces provided at a predetermined distance on either side of said external terminals to prevent crosstalk between said external terminals.
Claim 4
Dependent Claim
34 words
A semiconductor device according to claim 1, wherein each of said grounding surfaces are formed as metal planes extending from an internal portion of said semiconductor device to the vicinity of said external terminals.
Claim 5
Dependent Claim
41 words
A semiconductor device according to claim 2, wherein said grounding surfaces are formed as metal frames which surround the chip on said IC package and extend from an internal portion of said semiconductor device to the vicinity of said external terminals.
Claim 6
Dependent Claim
42 words
A semiconductor device according to claim 1, further comprising a plurality of a second set of signal lines coupling said external signals to said chip, each of said second set of signal lines being provided along the side surfaces of said device.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-02-15 | 1991-08-17 | 1992-02-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-02-15 | 1995-08-17 | 1996-02-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-02-15 | 1999-08-17 | 2000-02-16 | $7700.00 | Window Closed / Lapsed |