Series port connection of a plurality of terminals to a master processor

Claim 1

A circuit arrangement for connecting a plurality of digitally operated terminals to a single communications circuit of a master digital processing unit for transmission of information between the processing unit and the individual terminals, and where positive polarity voltage levels and certain negative polarity voltage levels represent a data segment of information to be transmitted and which data segments are identified by data start bits and data stop bits, and negative polarity voltage levels represent non-data signal levels, each said positive and negative polarity levels further being defined to exist in predetermined voltage ranges and with voltages between these ranges representing floating ground voltages, said circuit arrangement comprising: (a) a non-looped data delivery bus from said communications circuit having only one end terminating at said communications circuit for delivery of digital information from said processing unit to any of the individual terminals and not having the opposite end of said data delivery bus looped back to said communications circuit, (b) a non-looped data return bus from said communications circuit having only one end terminating at said communications circuit for delivery of digital information from any individual terminal to the processing unit and not having the opposite end of said data return bus looped back to said communications circuit, (c) connecting means connecting each of said individual terminals to said data delivery bus and data return bus so that each of said terminals are in a series arrangement with respect to said single communications circuit, and in parallel arrangement across said data delivery bus and data return bus, and (d) a line isolation circuit means operatively associated with said circuit arrangement and comprising a first component in each connecting means to permit a positive data signal voltage level on the data return bus without any other terminal simultaneously driving down the positive bit voltage level of that signal, and a second component in at least one of said connecting means connected to a negative polarity voltage source having a negative voltage in the predetermined voltage range to reduce the voltage level on that return line to a non-data signal level when data delivery has been completed.

Claim 14

A system for multiplexing digital information between a central master processing unit and a plurality of terminals serially connected to a communications circuit of that central master processing unit, said system comprising: (a) A first non-looped data bus from said communications circuit for delivery of information from said terminals to said processing unit or from said processing unit to said terminals, said first data bus having only one end connected to the communications circuit of said master processing unit but not having the opposite end of said first data bus looped back to said communications circuit of said master processing unit, (b) a second non-looped data bus from said communications circuit for delivery of information from said terminals to said processing unit or from said processing unit to said terminals, but in a direction opposite that of information on said first data line, said second data bus having only one end connected to the communications circuit of said master processing unit but not having the opposite end of said second data bus looped back to said communications circuit of said master processing unit, (c) the information for delivery between the terminals and the processing unit being characterized by positive polarity voltage bits of predefined voltage levels and negative polarity bits of the same predefined voltage magnitude as the positive polarity bits but of opposite polarity to represent segments of data to be transmitted and which segments are also defined by data start bits and data stop bits, and additional negative polarity voltage bits having substantially the same predefined voltage magnitude as the positive polarity bits but of opposite polarity to represent non-data signal levels, (d) a first conductor at each terminal connecting that terminal to said first data bus, (e) a second conductor at each terminal connecting that terminal to said second data bus so that each of the terminals are in a series arrangement with respect to the communications circuit and in a parallel arrangement across the first and second data busses, (f) a diode in the second conductor of each terminal between the terminal and the second conductor, said diode being oriented to prevent biasing of positive voltage data bits onto the first data bus and preventing such data bits from entering that terminal from the first data bus to thereby prevent any other terminal from reducing the selected positive voltage level, and (g) a pull-down resistor connected to the output of the diode on at least one of the terminals, and being connected to a negative polarity voltage source at the predefined negative polarity voltage to reduce the voltage on the first data bus to a non-data signal level when delivery of information has been completed.

Claim 15

A system for multiplexing digital information between a central master processing unit and a plurality of terminals serially connected to a communications circuit of that central master processing unit, said system comprising: (a) A first non-looped data bus from said communications circuit for delivery of information from said terminals to said processing unit or from said processing unit to said terminals, said first data bus having only one end connected to the communications circuit of said master processing unit but not having the opposite end of said first data bus looped back to said communications circuit of said master processing unit, (b) a second non-looped data bus from said communications circuit for delivery of information from said terminals to said processing unit or from said processing unit to said terminals, but in a direction opposite that of information on said first data line, said second data bus having only one end connected to the communications circuit of said master processing unit but not having the opposite end of said second data bus looped back to said communications circuit of said master processing unit, (c) the information for delivery between the terminals and the processing unit being characterized by positive polarity voltage bits of predefined voltage levels and negative polarity bits of the same predefined voltage magnitude as the positive polarity bits but of opposite polarity to represent segments of data to be transmitted and which segments are also defined by data start bits and data stop bits, and additional negative polarity voltage bits having substantially the same predefined voltage magnitude as the positive polarity bits but of opposite polarity to represent non-data signal levels, (d) a first conductor at each terminal connecting that terminal to said first data bus, (e) a second conductor at each terminal connecting that terminal to said second data bus so that each of the terminals are in a series arrangement with respect to the communications circuit and in a parallel arrangement across the first and second data busses, (f) a diode in the second conductor of each terminal between the terminal and the second conductor, said diode being oriented to prevent biasing of positive voltage data bits onto the first data bus and preventing such data bits from entering that terminal from the first data bus to thereby prevent any other terminal from reducing the selected positive voltage level, and (g) a pull-down resistor connected to the output of the diode on at least one of the terminals, and being connected to a negative polarity voltage source at the predefined negative polarity voltage to reduce the voltage on the first data bus to a non-data signal level when delivery of information has been completed.