Input buffer circuit and logic circuit using the buffer circuit

Claim 2

An input buffer circuit comprising: a input transistor receiving an input signal at its emitter electrode; an emitter-follower transistor receiving a signal at its base electrode from a collector electrode of said input transistor and providing an output signal at an emitter electrode of said emitter-follower transistor; voltage dividing resistors connected to a collector electrode of said input transistor and including a pair of resistors connected to each other in series for dividing a voltage of a signal at said collector electrode of said input transistor to produce a divided voltage signal; and a feedback circuit coupled to receive said divided voltage signal produced by said voltage dividing resistors and including means for providing a feedback signal path to feed back the divided voltage signal to a base electrode of said input transistor, said input buffer circuit further comprising at least one of a first capacitor connected in parallel to the feedback signal path of said feedback circuit, a second capacitor connected between the collector and emitter electrodes of said input transistor, and a third capacitor connected in parallel to said voltage dividing resistors.

Claim 3

An input buffer circuit according to claim 1, wherein said feedback circuit includes a transistor with its base electrode receiving a signal produced at a connection point of said voltage dividing resistors and with an emitter electrode connected to the base electrode of said input transistor; and a constant current source supplying a current to said transistor

Claim 4

An input buffer circuit according to claim 1 further comprising a clamping circuit connected in parallel to said voltage dividing resistors.

Claim 5

An input buffer circuit according to claim 3, wherein said clamping circuit comprises a transistor with its base and collector electrodes being connected together to one end of said voltage dividing resistors and with its emitter electrode being connected to another end of said dividing resistors.

Claim 6

An input buffer circuit according to claim 2, wherein said constant current source comprises a transistor with its base electrode being supplied with a bias voltage, with its emitter electrode being connected by a resistor to a negative voltage source, and with its collector electrode being connected to the base electrode of said input transistor.

Claim 7

An input buffer circuit according to claim 2, wherein said constant current source comprises a resistor connected between the base electrode of said input transistor and a negative voltage source.

Claim 8

A logic circuit comprising: an input multiemitter transistor having a plurality of emitter electrodes at which input signals are received; an emitter-follower transistor receiving a signal at its base electrode from a collector electrode of said input transistor and providing at its emitter electrode an output signal; voltage dividing resistors connected to a collector electrode of said input transistor and including a pair of resistors connected to each other in series for dividing a voltage of a signal at said collector electrode of said input transistor to produce a divided voltage signal; and a feedback circuit coupled to receive said divided voltage signal produced by said voltage dividing resistors and including means for providing a feedback signal path to feed back the divided voltage signal to a base electrode of said input transistor, wherein said feedback circuit comprises as transistor with its base electrode receiving the divided voltage signal produced at a connection point node of said voltage dividing resistors and with its emitter electrode being connected to the base electrode of said input transistor; and a constant current source supplying a current to said transistor, and wherein said logic circuit further comprises at least one of a first capacitor connected in parallel to the feedback signal path of said feedback circuit, a second capacitor connected between the collector and emitter electrodes of said input transistor, and a third capacitor connected in parallel to said voltage dividing resistors.

Claim 9

A logic circuit comprising: an input multiemitter transistor having a plurality of emitter electrodes at which input signals are received; an emitter-follower transistor receiving a signal at its base electrode from a collector electrode of said input transistor and providing at its emitter electrode an output signal; voltage dividing resistors connected to a collector electrode of said input transistor and including a pair of resistors connected to each other in series for dividing a voltage of a signal at said collector electrode of said input transistor to produce a divided voltage signal; and a feedback circuit coupled to receive said divided voltage signal produced by said voltage dividing resistors and including means for providing a feedback signal path to feed back the divided voltage signal to a base electrode of said input transistor, wherein said feedback circuit comprises as transistor with its base electrode receiving the divided voltage signal produced at a connection point node of said voltage dividing resistors and with its emitter electrode being connected to the base electrode of said input transistor; and a constant current source supplying a current to said transistor, and wherein said logic circuit further comprises at least one of a first capacitor connected in parallel to the feedback signal path of said feedback circuit, a second capacitor connected between the collector and emitter electrodes of said input transistor, and a third capacitor connected in parallel to said voltage dividing resistors.

Claim 10

A logic circuit according to claim 7, wherein said input multiemitter transistor provides a logical AND function for input signals applied to said emitter electrodes of said input transistor.

Claim 11

A logic circuit according to claim 7 further comprising a clamping circuit connected in parallel to said voltage dividing resistors.

Claim 12

A logic circuit according to claim 9, wherein said clamping circuit comprises a transistor with its base and collector electrodes being connected together to one end of said voltage dividing resistors and with its emitter electrode being connected to another end of said resistors.

Claim 13

A logic circuit according to claim 7, wherein said constant current source comprises a transistor with its base electrode being supplied with a bias voltage, with its emitter electrode being connected by a resistor to a negative voltage source, and with its collector electrode being connected to the base electrode of said input transistor.

Claim 14

A logic circuit according to claim 7, wherein said constant current source comprises a resistor connected between the base electrode of said input transistor and a negative voltage source.

Claim 15

A logic circuit comprising: an input terminal; a first circuit including an input transistor receiving an input signal at its emitter connected to said input terminal, voltage dividing resistors connected to a collector of said input transistor and including a pair of resistors connected to each other in series for dividing a voltage of a signal at said collector electrode of said input transistor to produce a divided voltage signal and a feedback circuit coupled to receive the divided voltage signal produced by said voltage dividing resistors and including means for providing a feedback signal path to feedback the divided voltage signal to a base of said input transistor; a first emitter-follower transistor receiving an input signal at its base from a collector of said input transistor of said first circuit and providing an output signal at its emitter; a second circuit producing an output signal to be supplied to an emitter-follower transistor; a second emitter-follower transistor receiving said output signal of said second circuit at its base and providing an output signal at its emitter; and an output terminal in which the emitters of said first and second emitter-follower transistors are mutually connected, said logic circuit further comprising at least one of a first capacitor connected in parallel to the feedback signal path of said feedback circuit, a second capacitor connected between the collector and emitter electrodes of said input transistor, and a third capacitor connected in parallel to said voltage dividing resistors.

Claim 16

A logic circuit comprising: an input terminal; a first circuit including an input transistor receiving an input signal at its emitter connected to said input terminal, voltage dividing resistors connected to a collector of said input transistor and including a pair of resistors connected to each other in series for dividing a voltage of a signal at said collector electrode of said input transistor to produce a divided voltage signal and a feedback circuit coupled to receive the divided voltage signal produced by said voltage dividing resistors and including means for providing a feedback signal path to feedback the divided voltage signal to a base of said input transistor; a first emitter-follower transistor receiving an input signal at its base from a collector of said input transistor of said first circuit and providing an output signal at its emitter; a second circuit producing an output signal to be supplied to an emitter-follower transistor; a second emitter-follower transistor receiving said output signal of said second circuit at its base and providing an output signal at its emitter; and an output terminal in which the emitters of said first and second emitter-follower transistors are mutually connected, said logic circuit further comprising at least one of a first capacitor connected in parallel to the feedback signal path of said feedback circuit, a second capacitor connected between the collector and emitter electrodes of said input transistor, and a third capacitor connected in parallel to said voltage dividing resistors.

Claim 17

A logic circuit according to claim 13, wherein said second circuit further comprises an input transistor receiving an input signal at the emitter electrode thereof and providing a signal at the collector electrode thereof to said output transistor, a voltage dividing resistor pair connected to the collector electrode of said input transistor, and a feedback circuit conducting a signal produced by said voltage dividing resistor pair back to the base electrode of said input transistor.