Phase unbalance detector

Claim 2

A polyphase alternating current line unbalance detector comprising: means for generating a pulse sequence having time separations from pulse to pulse determined by a balance condition of phase-to-neutral voltages for each said line; means, responsive to said pulse sequence, for generating a square wave having a predetermined width in time; means, responsive to said pulse sequence and responsive to said square wave, for generating an output voltage corresponding to a difference between said pulse sequence and said square wave; means for integrating said output voltage to generate an integrated voltage; and, means, responsive to said integrated voltage, for generating an output signal if said integrated voltage exceeds a predetermined value.

Claim 3

The apparatus as in claim 1 wherein said pulse sequence has a pulse spacing dependent upon the time between zero crossing intervals of said voltages on said polyphase alternating current lines, and said square wave has a time duration chosen as representative of said pulse spacing of said pulse sequence when said polyphase alternating current line voltages are balanced.

Claim 4

The apparatus as in claim 1 wherein said polyphase alternating current line is a three phase alternating curent line, and said means for generating a pulse sequence further comprised: a phase-to-neutral voltage generator having transformer secondaries (88) connected in an electrical wye connection and primaries of said transformers connected in an electrical delta connection; a resistor network (692) for effecting summation of predetermined amounts of said secondary transformer voltages; one comparator (698, 700, 702) connected to each said phase for generating square waves; and, means for combining an output of each said comparator to form said pulse sequence.

Claim 5

The apparatus as in claim 3 wherein said means for generating a pulse sequence further comprises: a first NOR gate (704), a second NOR gate (706), a third NOR gate (708), and a fourth NOR gate (710), said first NOR gate having a first input connected to said first comparator and a second input connected to said second comparator, and said second NOR gate having a first input connected to said second comparator and having a second input connected to said third comparator, and said third NOR gate having a first input connected to said third comparator and a second input connected to said first comparator, and said fourth NOR gate having a first input connected to the output of said first NOR gate, a second connected to the output of said second NOR gate, and a third input connected to an output of said third NOR gate, and an output of said fourth NOR gate providing a square wave as said logic waveform, said square wave having a transition corresponding to each zero crossing point of said phase-to-neutral voltages.

Claim 6

The apparatus as in claim 4 further comprising: a noise filter (376) connected to said means for generating a pulse sequence so that said noise filter provides said pulse sequence having reduced noise.

Claim 7

The apparatus as in claim 5 wherein said means for generating a square wave comprises: a one-shot circuit (732) triggered by an output of said noise filter, and having an output pulse whose width may be adjusted to a predetermined width.

Claim 8

The apparatus as in claim 1 wherein said means for generating an output voltage corresponding to a difference between said pulse sequence and said square wave further comprises: an exclusive OR gate (730) having a first input connected to receive said logic waveform, and having a second input connected to receive said standard waveform, and having an output pulse whose width depends upon the difference in widths of said logic waveform and said standard waveform; an integrator (742) for integrating said output pulses, said integrator having an integrating capacitor (C4) and a discharge resistor (R18); and, a voltage level detector (740) for generating an output signal when an output of said integrator exceeds a predetermined voltage.

Claim 9

Means for generating an output signal as in claim 7, further comprising: a NOR gate (738) for disabling said integrator in the absence of a start signal or in the absence of an up-to-speed signal when said polyphase alternating current line unbalance detector is used for controlling an electric motor.

Claim 10

The apparatus as in claim 1 wherein said polyphase alternating current line is a three phase alternating current line.

Claim 11

The apparatus as in claim 1 wherein said means for generating an output voltage corresponding to a difference between said pulse sequence and said square wave compares every other cycle of said logic waveform with said standard waveform, and is inactive during in-between cycles of said pulse sequence.

Claim 12

A three phase alternating current line unbalance detector comprising: a representing waveform generator having a phase-to-neutral voltage for each said line, a clipping circuit for each said phase-to-neutral voltage to generate said representative waveform as a square wave for each said phase-to-neutral voltage; a logic circuit, responsive to said representative waveforms, for generating a logic waveform having a transition corresponding to each zero crossing of said phase to neutral voltages; a circuit, responsive to said logic waveform, for generating a standard waveform having an output pulse width which may be adjusted to a predetermined width; a comparator for comparing said logic waveform and said standard waveform for generating a train of pulses, each said pulse in said train of pulses having a width substantially equal to the difference in widths of said logic waveform and said standard waveform; an integrator for integrating said train of pulses to provide a voltage level responsive to the cumulative widths of a train of said pulses; and a voltage level detector for generating an output signal when said voltage level of said integrator exceeds a predetermined voltage, said output signal indicating that an unbalance in said three phase alternating current line has been detected.

Claim 13

A three phase alternating current line unbalance detector comprising: a representing waveform generator having a phase-to-neutral voltage for each said line, a clipping circuit for each said phase-to-neutral voltage to generate said representative waveform as a square wave for each said phase-to-neutral voltage; a logic circuit, responsive to said representative waveforms, for generating a logic waveform having a transition corresponding to each zero crossing of said phase to neutral voltages; a circuit, responsive to said logic waveform, for generating a standard waveform having an output pulse width which may be adjusted to a predetermined width; a comparator for comparing said logic waveform and said standard waveform for generating a train of pulses, each said pulse in said train of pulses having a width substantially equal to the difference in widths of said logic waveform and said standard waveform; an integrator for integrating said train of pulses to provide a voltage level responsive to the cumulative widths of a train of said pulses; and a voltage level detector for generating an output signal when said voltage level of said integrator exceeds a predetermined voltage, said output signal indicating that an unbalance in said three phase alternating current line has been detected.

Claim 14

A three phase alternating current line unbalance detector comprising: a representative waveform generator having a phase-to-neutral voltage generator for each said line, said phase-to-neutral voltage generator having a voltage for each said line from transformer secondaries (88), said transformer secondaries being connected in an electrical wye connection and primaries of said transformers being connected in an electrical delta connection, and a resistor network (692) for effecting summation of predetermined amounts of said secondary transformer voltages in order to generate said phase-to-neutral voltages, and a first comparator (698), a second comparator (700), and a third comparator (702), one comparator for each said phase-to-neutral voltage, for generating a square wave for each phase-to-neutral voltage, each said square wave to serve as said representative waveform for its respective said phase-to-neutral voltage; a logic waveform generator, responsive to said representative waveforms, having a first NOR gate (704), a second NOR gate (706), a third NOR gate (708), and a fourth NOR gate (710), said first NOR gate having a first input connected to said first comparator, and a second input connected to said second comparator, and said second NOR gate having a first input connected to said second comparator and having a second input connected to said third comparator, and said third NOR gate having a first input connected to said third comparator and a second input connected to said first comparator, and said fourth NOR gate having a first input connected to an output of said first NOR gate, a second input connected to an output of said second NOR gate, and a third input connected in an output of said third NOR gate, and an output of said fourth NOR gate providing a square wave as said logic waveform, said square wave having a transition corresponding to each zero crossing of said phase-to-neutral voltages; a standard waveform generator having a one-shot circuit (732) triggered by said logic waveform, and having an output pulse whose width may be adjusted to a predetermined width; an output signal generator having an exclusive OR gate (730) having a first input connected to receive said said logic waveform, and having a second input connected to receive said standard waveform, and having an output pulse whose width depends upon the difference in widths of said logic waveform and said standard waveform; an integrator (742) for integrating said output pulses to provide a voltage level responsive to the cumulative widths of a train of said pulses; and, a voltage level detector (740) for generating an output signal when said voltage level of said integrator exceeds a predetermined voltage, said output signal indicating that a unbalance in said three phase alternating current line has been detected.

Claim 15

A three phase alternating current line unbalance detector comprising: a representative waveform generator having a phase-to-neutral voltage generator for each said line, said phase-to-neutral voltage generator having a voltage for each said line from transformer secondaries (88), said transformer secondaries being connected in an electrical wye connection and primaries of said transformers being connected in an electrical delta connection, and a resistor network (692) for effecting summation of predetermined amounts of said secondary transformer voltages in order to generate said phase-to-neutral voltages, and a first comparator (698), a second comparator (700), and a third comparator (702), one comparator for each said phase-to-neutral voltage, for generating a square wave for each phase-to-neutral voltage, each said square wave to serve as said representative waveform for its respective said phase-to-neutral voltage; a logic waveform generator, responsive to said representative waveforms, having a first NOR gate (704), a second NOR gate (706), a third NOR gate (708), and a fourth NOR gate (710), said first NOR gate having a first input connected to said first comparator, and a second input connected to said second comparator, and said second NOR gate having a first input connected to said second comparator and having a second input connected to said third comparator, and said third NOR gate having a first input connected to said third comparator and a second input connected to said first comparator, and said fourth NOR gate having a first input connected to an output of said first NOR gate, a second input connected to an output of said second NOR gate, and a third input connected in an output of said third NOR gate, and an output of said fourth NOR gate providing a square wave as said logic waveform, said square wave having a transition corresponding to each zero crossing of said phase-to-neutral voltages; a standard waveform generator having a one-shot circuit (732) triggered by said logic waveform, and having an output pulse whose width may be adjusted to a predetermined width; an output signal generator having an exclusive OR gate (730) having a first input connected to receive said said logic waveform, and having a second input connected to receive said standard waveform, and having an output pulse whose width depends upon the difference in widths of said logic waveform and said standard waveform; an integrator (742) for integrating said output pulses to provide a voltage level responsive to the cumulative widths of a train of said pulses; and, a voltage level detector (740) for generating an output signal when said voltage level of said integrator exceeds a predetermined voltage, said output signal indicating that a unbalance in said three phase alternating current line has been detected.