Signal acquisition circuit with variable bandwidth phase locked loop

Claim 1

A signal acquisition circuit for a radar system, comprising: (a) a phase lock loop to which an input signal is applied; (b) a variable frequency oscillator in the phase lock loop, said oscillator having a signal output; (c) means for locking the frequency of said variable frequency oscillator; (d) comparison means arranged to determine the magnitude of a part of the input signal within the bandwidth of the phase lock loop and in phase coherence with the variable frequency oscillator, and to provide an output signal indicative of said magnitude; (e) means for varying the bandwidth of the phase lock loop in accordance with the output signal from the comparison means until the bandwidth stabilizes and the output signal of the comparison means is brought to a first predetermined value; (f) first detection means arranged to produce an output signal dependent on whether the output signal from the comparison means is above or below a second predetermined value when said bandwidth stabilizes; and (g) a confirm trigger circuit and a reject trigger circuit connected to receive the output signal from the first detection means, the confirm trigger circuit being arranged to produce a confirm target signal if the phase lock loop stabilizes at a relatively narrow bandwidth, and the reject trigger circuit being arranged to produce a reject signal if the phase lock loop stabilizes at a relatively broad bandwidth.