US4724422A
Expired / Lapsed
US
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Redundant decoder
Assignee: Motorola Solutions Inc
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Filing: 1985-09-13
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Granted: 1988-02-09
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Expires: 2005-09-13
Abstract
Abstract A redundant decoder for use in a predecoded memory scheme includes a plurality of predecoding circuits each having an output and each having inputs coupled to selected address signals. The outputs of the predecoding circuits are applied to the inputs of a smaller group of decoding circuit. In addition, the outputs of the predecoding circuits are coupled to the gate electrodes of one of a plurality of series coupled field effect transistors each having a laser blowable fuse coupled across its source drain path. Should one of the decoding circuits prove to be operating improperly, is only necessary to blow the fuses across the individual field effect transistors whose gate electrodes are coupled to the predecoding circuit outputs which served as inputs to the bad gate. In this manner, the output of the stack will go high only when the output of the bad decoding circuit should go high.
Inventors
- 👤 James S. Golab
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 11:03
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/80; G11C8/00; G11C8/10
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
134 words
A redundant decoder for use in a memory system, comprising: a first plurality of predecoding logic means each having an output and each having at least one input for receiving one of a plurality of address signals capable of assuming at least first and second states; a second smaller plurality of logic means each having an output and each having inputs coupled to selected ones of the output of said first plurality of predecoding logic means; a first plurality of switching devices coupled in series between first and second supply voltage terminals, each having a control terminal coupled to receive one of the outputs of said first plurality of predecoding logic means; and a plurality of selectively removable conducting devices each one coupled in parallel with one of said second plurality of switching devices.
Claim 2
Dependent Claim
134 words
A redundant decoder for use in a memory system, comprising: a first plurality of predecoding logic means each having an output and each having at least one input for receiving one of a plurality of address signals capable of assuming at least first and second states; a second smaller plurality of logic means each having an output and each having inputs coupled to selected ones of the output of said first plurality of predecoding logic means; a first plurality of switching devices coupled in series between first and second supply voltage terminals, each having a control terminal coupled to receive one of the outputs of said first plurality of predecoding logic means; and a plurality of selectively removable conducting devices each one coupled in parallel with one of said second plurality of switching devices.
Claim 3
Dependent Claim
20 words
A decoder according to claim 1 wherein the selectively removable conducting devices are fuses which are removed be being blown.
Claim 4
Dependent Claim
33 words
A decoder according to claim 1 wherein each of said switching devices is a field-effect transistor having source and drain electrodes and wherein said control terminal comprises the gate electrode of said field-effect-transistor.
Claim 5
Dependent Claim
35 words
A decoder according to claim 3 wherein each of said selectively removable conducting devices comprises a laser blowable fuse coupled in parallel between the source and drain electrodes of at least one of said field-effect-transistors.
Claim 6
Dependent Claim
20 words
A decoder according to claim 4 further comprising first means for enabling and disabling said first plurality of switching devices.
Claim 7
Dependent Claim
74 words
A decoder according to claim 5 wherein said first means comprises: voltage pull-down means coupled between said first supply voltage terminal and a first end of said third plurality of series coupled switching devices; and voltage pull-up means coupled between said second supply voltage terminal and a second end of said first plurality of series coupled switching devices, said voltage pull-up means and said voltage pull-down means coupled to receive an enable control signal.
Claim 8
Dependent Claim
45 words
A decoder according to claim 6 wherein said voltage pull-down means comprises a first field-effect-transistor having a first electrode coupled to said first supply voltage terminal, a second electrode coupled to said first end, and a gate electrode for coupling to said enable control signal.
Claim 9
Dependent Claim
45 words
A decoder according to claim 7 wherein said voltage pull-up means comprises a second field-effect-transistor having a first electrode coupled to said second supply voltage terminal, a second electrode coupled to said second end, and a gate electrode for coupling to said enable control signal.
Claim 10
Dependent Claim
33 words
A decoder according to claim 8 wherein each of said first plurality of switching device and said first field-effect-transistor are of the N-channel type, and said second field-effect-transistor is of the P-channel type.
References Cited (Backward Citations)
US4590388A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-02-08 | 1991-08-10 | 1992-02-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-02-08 | 1995-08-10 | 1996-02-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-02-08 | 1999-08-10 | 2000-02-09 | $7700.00 | Window Closed / Lapsed |