Method and apparatus for quasi-analog reconstructions of amplitude and frequency varying analog input signals

Claim 2

In a method for producing a high level quasi-analog reconstruction of an amplitude and frequency varying analog input signal, wherein the analog input signal is quantized to deliver C parallel binary bits representing each quantized value of said analog input signal in pulse code, the improvement comprising: (a) carrying out a binary-to-discrete decimal step conversion of A major bits of said C parallel binary bits, said C parallel bits consisting of B minor bits plus said A major bits to satisfy the relation A+B=C, for outputting (2 A -1) parallel discrete decimal data bits; (b) utilizing said (2 A -1) decimal data bits to respectively supply equal electrical voltages in response thereto, each voltage being of a magnitude V c , where ##EQU5## and V max is substantially the peak voltage to be provided in said high level quasi-analog reconstruction of said analog input signal; (c) utilizing N MSB's of said B minor bits to respectively supply electrical voltages which decline in one-half voltage increments from Vc/2 to Vc/2 N ; (d) utilizing the combination of the remaining (B-N) LSB's of said B minor bits to supply electrical voltages which decline in one-half voltage increments and which, from the highest to the lowest binary value of said combination of (B-N) LSB's, range from Vc/2 N+1 to Vc/2 B ; and (e) additively combining, in each quantization period, all electrical voltages supplied by the utilization of said (2 A -1) decimal data bits and by the utilization of said N MSB's and said (B-N) LSB's of said B minor bits, thereby to produce said quasi-analog reconstruction of said analog input signal.

Claim 3

In an apparatus for producing a high level quasi-analog reconstruction of an amplitude and frequency varying analog input signal, including quantizer means having input terminals for receiving the analog input signal and a plurality of C output terminals for respectively delivering C parallel binary bits representing a quantized value of said analog input signal in pulse code, the improvement comprising: (a) a binary-to-discrete decimal step converter having a plurality of A input terminals for respectively receiving A major bits of said C parallel binary bits, said C parallel binary bits consisting of B minor bits plus said A major bits to satisfy the relation A+B=C, said converter having a plurality of (2 A -1) output terminals for respectively outputting (2 A -1) discrete decimal data bits; (b) a plurality of (2 A -1) discrete power sources connected to said converter output terminals and respectively controlled by said (2 A -1) discrete decimal data bits to respectively supply electrical voltages in response thereto, each voltage being of a magnitude V c equal for all said (2 A -1) discrete power sources, where ##EQU6## and V max is substantially the peak voltage to be provided in said high level quasi-reconstruction of said analog input signal; (c) a plurality of other power sources of two kinds, one kind being discrete power sources respectively controlled by N MSB's of said B minor bits to respectively supply electrical voltages which decline in one-half voltage increments from Vc/2 to Vc/2 N , the second kind being a single power source controlled by the combination of the remaining (B-N) LSB's of said B minor bits to supply electrical voltages which decline in one-half voltage increments and which, from the highest to the lowest binary value of said (B-N) LSB's, range from Vc/(2 N+1 ) to Vc/2 B ; and (d) means connected to all of said power sources for additively combining the electrical voltages controllably supplied by said sources in each quantization period, thereby to produce said quasi-analog reproduction of said analog input signal.

Claim 4

In an apparatus for producing a high level quasi-analog reconstruction of an amplitude and frequency varying analog input signal, including quantizer means having input terminals for receiving the analog input signal and a plurality of C output terminals for respectively delivering C parallel binary bits representing a quantized value of said analog input signal in pulse code, the improvement comprising: (a) a binary-to-discrete decimal step converter having a plurality of A input terminals for respectively receiving A major bits of said C parallel binary bits, said C parallel binary bits consisting of B minor bits plus said A major bits to satisfy the relation A+B=C, said converter having a plurality of (2 A -1) output terminals for respectively outputting (2 A -1) discrete decimal data bits; (b) a plurality of (2 A -1) discrete power sources connected to said converter output terminals and respectively controlled by said (2 A -1) discrete decimal data bits to respectively supply electrical voltages in response thereto, each voltage being of a magnitude V c equal for all said (2 A -1) discrete power sources, where ##EQU6## and V max is substantially the peak voltage to be provided in said high level quasi-reconstruction of said analog input signal; (c) a plurality of other power sources of two kinds, one kind being discrete power sources respectively controlled by N MSB's of said B minor bits to respectively supply electrical voltages which decline in one-half voltage increments from Vc/2 to Vc/2 N , the second kind being a single power source controlled by the combination of the remaining (B-N) LSB's of said B minor bits to supply electrical voltages which decline in one-half voltage increments and which, from the highest to the lowest binary value of said (B-N) LSB's, range from Vc/(2 N+1 ) to Vc/2 B ; and (d) means connected to all of said power sources for additively combining the electrical voltages controllably supplied by said sources in each quantization period, thereby to produce said quasi-analog reproduction of said analog input signal.