US3581076A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital to analog current distribution circuit
Assignee: Unisys Corp
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Filing: 1969-07-17
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Granted: 1971-05-25
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Expires: 1989-07-17
Abstract
Abstract A current distribution circuit suitable for use in a digital-toanalog converter in which digital signals are applied either directly or through a logic network to selected flip-flop stages such that the flip-flops produce a number of output signals which individually represent a given increment of current. These current increments are made available to a resistive ladder type current metering circuit to produce the desired analog voltage.
Inventors
- 👤 Mauritz L Granberg
- 👤 Hubert W Mueller Jr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:19
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/06; H03M1/0617
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
135 words
A current distribution circuit for receiving first and second bits of digital information representing first increments of current from a storage means and producing output signals representing second increments of current, said circuit comprising: a. a first group of n+p bistable circuits coupled to said storage means for receiving n of j first bits and p second bits and producing output signals representing unit increments of current where n>0, p>0 and i is an integer > 1, b. a logic circuit coupled to said storage means for receiving the remaining j-n first bits and producing r control signals where r 2j n-1, and c. a second group of r bistable circuits coupled to said logic circuit for receiving said r control signals and producing r output signals each representing an increment of current I where
Claim 2
Dependent Claim
135 words
A current distribution circuit for receiving first and second bits of digital information representing first increments of current from a storage means and producing output signals representing second increments of current, said circuit comprising: a. a first group of n+p bistable circuits coupled to said storage means for receiving n of j first bits and p second bits and producing output signals representing unit increments of current where n>0, p>0 and i is an integer > 1, b. a logic circuit coupled to said storage means for receiving the remaining j-n first bits and producing r control signals where r 2j n-1, and c. a second group of r bistable circuits coupled to said logic circuit for receiving said r control signals and producing r output signals each representing an increment of current I where
References Cited (Backward Citations)
US3134098A
Cited
US3305855A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-24 | 1974-11-23 | 1975-05-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-24 | 1978-11-23 | 1979-05-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-24 | 1982-11-23 | 1983-05-25 | $7700.00 | Window Closed / Lapsed |