Micro computer system

Claim 2

A microcomputer system, comprising: first central processing unit means having first input/output addresses; first memory means connected to said first central processing unit means; input/output means connected to said first central processing unit means for inputting data thereto and outputting data therefrom at respective addresses corresponding to said first input/output addresses and producing input/output control signals; second central processing unit means having second input/output addresses; second memory means connected to said second central processing unit means; first signal bus means operably connecting said first central processing unit means, said first memory means and said input/output means; second signal bus means operably connecting said second central processing unit means and said second memory means; and means connected to said first and second signal bus means and receiving over said first signal bus means said first input/output addresses of said first central processing unit means and said input/output control signals from said input/output means for mapping said second central processing unit means onto a selected one of said first input/output addresses of said first central processing unit means by placing said first and second signal bus means in data communication and including bus priority encoder means operably connected to said first and second signal bus means to give said first central processing unit means bus priority over said second central processing unit means with respect to both said first and second signal bus means.

Claim 3

A microcomputer system according to claim 1, in which said means for mapping said second central processing unit means onto a selected one of said first input/output addresses of said first central processing unit means by placing said first and second signal bus means in data communication includes signal generating means receiving selected said first input/output address of said first central processing unit means and said input/output control signals and producing decoding output signals therefrom, transceiver means operable in response to said decoding output signals for selectively connecting said frist and second signal bus means and determining the direction of data flow therebetween, data latch means operable in response to said decoding output signals and recieving data output from said first central processing unit means for supply to said second signal bus means, and bus driver means connected between said first and second signal bus means for passing data therebetween.

Claim 4

A microcomputer system according to claim 1, in which said means for mapping said second processing unit means onto a selected one of said first input/output addresses of said first central processing unit means includes signal generating means receiving at least said selected first input/output address of said first central processing unit means and said input/output control signals for decoding said selected first input/output address and producing a gating signal and a data direction signal, and transceiver means receiving said gating signal and said data direction signal and arranged to connect said first signal bus means with said second signal bus means and connected to be gated by said gating signal so that data flows between said first and second signal bus means in a direction responsive to said direction signal.

Claim 5

A microcomputer system according to claim 3, in which said signal generating means further produces latch clock signals from said first input/output addresses, and said means for mapping said second central processing unit means onto a selected one of said first input/output addresses of said first central processing unit means further includes data latch means connected between said first signal bus means and said second signal bus means for passing data therebetween in response to said latch clock signals, and bus driver means connected between said first signal bus means and said second signal bus means for passing data therebetween.

Claim 6

A microcomputer system according to claim 3, in which said bus priority encoder means includes first and second bus arbiter means connected to said first signal bus means and said second signal bus means, respectively, for controlling access to said first and second memory means for data transferred thereto, and a priority encoder connected to said first and second bus arbiter means for providing said first central processing unit means with said bus priority over said second central processing unit means when data is transferred to said first and second memory means at substantially the same time.

Claim 7

A microcomputer system according to claim 1, wherein said bus priority encoder means connected to said first and second signal bus means controls data flow therein, and includes bus arbiter means for controlling access to said first and second memory means for data transferred thereto, bus control means connected to said first and second signal bus means, and status signal generator means for generating status signals fed to enable said bus arbiter means that is connected to said first and second signal bus means and to enable said bus control means that is connected to said second signal bus means.

Claim 8

A microcomputer system according to claim 1, in which said first signal bus means includes a separate data bus, a separate address bus parallel to said data bus, and a separate control bus parallel to said address bus.

Claim 9

A microcomputer system according to claim 1, in which said first memory means includes a random access memory connected to said first central processing unit means and a read only memory connected to said first central processing unit means.

Claim 10

A microcomputer system according to claim 1, in which said second memory means includes a random access memory connected to said second central processing unit means and a read only memory connected to said second central processing means.

Claim 11

A microcomputer system according to claim 1, further comprising signal generating means connected to said first signal bus means for decoding at least said selected first input/output address mapped onto said first central processing unit means and producing a gating signal and a direction signal, and transceiver means receiving said gating signal and said direction signal, said transceiver means being included in said means for mapping said second central processing unit means onto a selected one of said first input/output addresses of said first central processing unit means, said gating signal and said direction signal being fed to said transceiver means for gating said transceiver means and determining the direction of data flow so that data can be transferred between said first and second central processing unit means without conflict.

Claim 12

A microcomputer system, comprising: host computer means including first central processing unit means having data terminals and address terminals, and input/output means connected to said data and address terminals for inputting data and outputting data at respective input/output addresses of said first and central processing unit means and producing input/output control signals; first memory means connected to said first central processing unit means; second central processing unit means having data terminals and address terminals and being devoid of respective input/output means for inputting/outputting data; second memory means connected to said second central processing unit means; first bus means for operably connecting said first central processing unit means, said input/output means, and said first memory means; second bus means for operably connecting said second processing means unit and said second memory means; and means connected to said first and second bus means and receiving input/output addresses of said first central processing unit means and said input/output control signals from said input/output means for mapping said second central processing unit means onto a selected one of said input/output addresses of said first central processing unit means by placing said first and second bus means in data communication and including a bus priority encoder means connected to said first and second bus means and operating to provide said first central processing unit with bus priority over said second central processing unit with respect to said first and second data bus means.

Claim 13

A microcomputer system, comprising: host computer means including first central processing unit means having data terminals and address terminals, and input/output means connected to said data and address terminals for inputting data and outputting data at respective input/output addresses of said first and central processing unit means and producing input/output control signals; first memory means connected to said first central processing unit means; second central processing unit means having data terminals and address terminals and being devoid of respective input/output means for inputting/outputting data; second memory means connected to said second central processing unit means; first bus means for operably connecting said first central processing unit means, said input/output means, and said first memory means; second bus means for operably connecting said second processing means unit and said second memory means; and means connected to said first and second bus means and receiving input/output addresses of said first central processing unit means and said input/output control signals from said input/output means for mapping said second central processing unit means onto a selected one of said input/output addresses of said first central processing unit means by placing said first and second bus means in data communication and including a bus priority encoder means connected to said first and second bus means and operating to provide said first central processing unit with bus priority over said second central processing unit with respect to said first and second data bus means.

Claim 14

A microcomputer system according to claim 11, in which said means for mapping said second central processing unit means onto a selected one of said input/output addresses of said first central processing unit means includes signal generating means receiving at least said selected input/output address of said first central processing means and said input/output control signals and producing decoding output signals therefrom, transceiver means receiving data from said first central processing unit means for selectively connecting said first and second bus means for data flow therebetween and determining the direction of said data flow in response to said decoding output signals, data latch means operable in response to said decoding output signals from said decoder means and receiving data from said first central processing unit for connection to said second bus means, and bus driver means for coupling selected data between said first and second bus means.

Claim 15

A microcomputer system according to claim 12, further comprising decoder means connected to said first bus means for decoding address information from said first central processing unit means and producing a gating signal and a direction signal fed to said transceiver means whereby data is controllable transferred between said first and second memory means.

Claim 16

A microcomputer system according to claim 11, in which said bus priority encoder means includes first and second bus arbiter means connected to said first and said second bus means, respectively, for controlling access of data transferred to said first and second memory means, and a priority encoder connected to said first and second bus arbiter means for providing said first central processing unit means with bus priority over said second central processing unit means when data is transferred to said first and second memory means substantially simultaneously.

Claim 17

A microcomputer system according to claim 13, in which said first bus means includes a separate data bus, a separate address bus parallel to said data bus, and a separate control bus parallel to said address bus.

Claim 18

A microcomputer system according to claim 11, in which said first memory means includes a random access memory and a read only memory each connected to said first central processing unit means including input/output means.

Claim 19

A microcomputer system according to claim 1, in which said second memory means includes a random access memory and a read only memory each connected to said second central processing unit means not including an input/output means.