Semiconductor device having a programmable fuse element

Claim 2

A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a metal oxide semiconductor (MOS) transistor formation region in said semiconductor substrate, said MOS transistor formation region having a number of MOS transistors; an insulation layer provided on a region of said substrate, said region being located apart from said MOS transistor formation region; a fuse element provided on said insulation layer, said fuse element being connected to one of a source and a drain of one of said MOS transistors, said fuse element being destructible whereupon minority and majority carriers are released into said semiconductor substrate; a first semiconductor guard ring region of a second coductivity type formed in said semiconductor substrate, said first guard ring region surrounding said insulation layer; a second semiconductor guard ring region of said first conductivity type formed in said substrate, said second guard ring region surrounding said first guard ring region and spatially separated from said first guard ring region; and means for applying a voltage between said first and second guard ring regions so as to impress a reverse bias voltage between said first semiconductor guard ring region and said semiconductor substrate, said first and second guard ring regions absorbing said minority and majority carriers, respectively, upon destruction of said fuse element.

Claim 3

The semiconductor device according to claim 1, wherein said second semiconductor guard ring region has an impurity concentration of at least 10 18 cm -3 .

Claim 4

The semiconductor device according to claim 1, wherein said fuse element is of a current melting type.

Claim 5

The semiconductor device according to claim 1, wherein said fuse element is of a laser interrupting type.

Claim 6

The semiconductor device according to claim 1, wherein said fuse element is of a laser shortcircuiting type.

Claim 7

The semiconductor device according to claim 1, wherein said fuse element is of the same material as a gate electrode material of said MOS transistors in said MOS transistor formation region.

Claim 8

The semiconductor device according to claim 1, wherein the thickness of said insulation layer on which said fuse element is formed is greater than that of a gate insulation film of said MOS transistors in said MOS transistor formation region.

Claim 9

A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a metal oxide semiconductor (MOS) transistor formation region in said semiconductor substrate, said MOS transistor formation region having a plurality of MOS transistors; a semiconductor well region of a second conductivity type in said substrate, said semiconductor well region being located apart from said MOS transistor formation region; an insulation layer provided on said semiconductor well region; a fuse element provided on said insulation layer, said fuse element being connected to one of a source and a drain of one of said MOS transistors, said fuse element being destructible whereupon minority and majority carriers are released into said semiconductor substrate; a first semiconductor guard ring region of a second conductivity type formed in said well region, said first guard ring region surrounding said insulation layer; a second semiconductor guard ring region of said first conductivity type formed in said substrate, said second guard ring region surrounding said first guard ring region and spatially separated from said first guard ring region; and means for applying a voltage between said first and second guard ring regions so as to impress a reverse bias voltage between said semiconductor well region and said semiconductor substrate, said first and second guard ring regions absorbing said minority and majority carriers, respectively, upon destruction of said fuse element.

Claim 10

A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a metal oxide semiconductor (MOS) transistor formation region in said semiconductor substrate, said MOS transistor formation region having a plurality of MOS transistors; a semiconductor well region of a second conductivity type in said substrate, said semiconductor well region being located apart from said MOS transistor formation region; an insulation layer provided on said semiconductor well region; a fuse element provided on said insulation layer, said fuse element being connected to one of a source and a drain of one of said MOS transistors, said fuse element being destructible whereupon minority and majority carriers are released into said semiconductor substrate; a first semiconductor guard ring region of a second conductivity type formed in said well region, said first guard ring region surrounding said insulation layer; a second semiconductor guard ring region of said first conductivity type formed in said substrate, said second guard ring region surrounding said first guard ring region and spatially separated from said first guard ring region; and means for applying a voltage between said first and second guard ring regions so as to impress a reverse bias voltage between said semiconductor well region and said semiconductor substrate, said first and second guard ring regions absorbing said minority and majority carriers, respectively, upon destruction of said fuse element.

Claim 11

A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a metal oxide semiconductor (MOS) transistor formation region in said substrate, said MOS transistor formation region having a plurality of MOS transistors; a semiconductor well region of a second conductivity type formed in said substrate, said semiconductor well region being located apart from said MOS transistor formation region; an insulation layer provided on said semiconductor well region; a fuse element provided on said insulation layer, said fuse element being connected to one of a source and a drain of one of said MOS transistors, said fuse element being destructible whereupon minority and majority carriers are released into said semiconductor substrate; a first semiconductor guard ring region of said first conductivity type formed in said semiconductor well region, said first guard ring region surrounding said insulation layer; a second semiconductor guard ring region of a second conductivity type formed in said well region, said second guard ring region surrounding said first guard ring region and spatially separated from said first guard ring region; and means for applying a voltage between said first and second guard ring regions so as to impress a reverse bias voltage between said semiconductor well region and said first guard ring region, said first and second guard ring regions absorbing said minority and majority carriers, respectively, upon destruction of said fuse element.

Claim 12

A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a metal oxide semiconductor (MOS) transistor formation region in said substrate, said MOS transistor formation region having a plurality of MOS transistors; a semiconductor well region of a second conductivity type formed in said substrate, said semiconductor well region being located apart from said MOS transistor formation region; an insulation layer provided on said semiconductor well region; a fuse element provided on said insulation layer, said fuse element being connected to one of a source and a drain of one of said MOS transistors, said fuse element being destructible whereupon minority and majority carriers are released into said semiconductor substrate; a first semiconductor guard ring region of said first conductivity type formed in said semiconductor well region, said first guard ring region surrounding said insulation layer; a second semiconductor guard ring region of a second conductivity type formed in said well region, said second guard ring region surrounding said first guard ring region and spatially separated from said first guard ring region; and means for applying a voltage between said first and second guard ring regions so as to impress a reverse bias voltage between said semiconductor well region and said first guard ring region, said first and second guard ring regions absorbing said minority and majority carriers, respectively, upon destruction of said fuse element.