CMOS integrated circuit protected from latch-up phenomenon

Claim 2

A CMOS integrated circuit device comprising: a first semiconductor substrate: first and second power supplying nodes; first and second channel types of MOS field effect transistors formed in said first semiconductor substrate, said MOS field effect transistors constituting an electrical circuit energized by power supplied between said first and second power supplying nodes; first and second power supplying terminals receiving an external power voltage therebetween, said second power supplying terminal being connected to said second power supplying node; and a second semiconductor substrate physically separate from said first semiconductor substrate and having formed therein a power control circuit which is electrically interposed between said first power supplying node and said first power supplying terminal, said power control circuit including means for detecting a decrease in a resistance component of said electrical circuit between said first and second power supplying nodes and means for decreasing power to be supplied to said electrical circuit when said resistance component is lower than a predetermined value.

Claim 3

A CMOS integrated circuit as claimed in claim 1, wherein said first semiconductor substrate is of a first conductivity type and has a well region of a second conductivity type, said first channel type MOS field effect transistors being formed in said first semiconductor substrate and said second channel type MOS field effect transistor being formed in said well region.

Claim 4

A CMOS integrated circuit as claimed in claim 2, wherein said power control circuit comprises a flip-flop circuit including first and second MOS field effect transistors having sources commonly connected to said first power supplying terminal, and a resistor, one end of said resistor being connected with the drain of said first MOS field effect transistor and the gate of said second MOS field effect transistor, the other end of said resistor being connected with said second power supplying terminal, and said second power supplying node being connected to the drain of said second MOS field effect transistor and the gate of said first MOS field effect transistor.

Claim 5

A CMOS integrated circuit device comprising: first and second semiconductor substrates of one conductivity type; a well region of another conductivity type formed in said first semiconductor substrate; a first insulated gate field effect transistor of a first channel type having source and drain regions of said another conductivity type formed in said first semiconductor substrate and a gate electrode formed on said first semiconductor substrate between said source and drain regions; a second insulated gate field effect transistor of a second channel type having source and drain regions of said one conductivity type formed in said well region and a gate electrode formed on said well region between said source and drain regions of said second insulated gate field effect transistor; third and fourth insulated gate field effect transistors of said first channel type having source and drain regions of said another conductivity type formed in said second semiconductor substrate and gate electrodes form on said second semiconductor substrate between said source and drain regions of said third and fourth insulated gate field effect transistors; a resistor region of said another conductivity type formed in said second semiconductor substrate and having first and second end portions; first and second power terminals supplied with a power voltage therebetween; means for connecting said gate electrodes of said first and second insulated gate field effect transistors to receive an input signal; means for connecting said drain regions of said first and second insulated gate field effect transistors to produce an output signal; means for connecting said source regions of said third and fourth insulated gate field effect transistors, said second semiconductor substrate and said first power terminal; means for connecting said gate electrode of said third insulated gate field effect transistor, said drain region of said fourth insulated gate field effect transistor and said first end portion of said resistor region; means for connecting said drain region of said third insulated gate field effect transistor, said gate electrode of said fourth insulated gate field effect transistor, said source region of said first insulated gate field effect transistor and said first semiconductor substrate; and means for connecting said source region of said second insulated gate field effect transistor, said well region, said second end of said resistor region, and said second power terminal.

Claim 6

A CMOS integrated circuit device comprising: first and second semiconductor substrates of one conductivity type; a well region of another conductivity type formed in said first semiconductor substrate; a first insulated gate field effect transistor of a first channel type having source and drain regions of said another conductivity type formed in said first semiconductor substrate and a gate electrode formed on said first semiconductor substrate between said source and drain regions; a second insulated gate field effect transistor of a second channel type having source and drain regions of said one conductivity type formed in said well region and a gate electrode formed on said well region between said source and drain regions of said second insulated gate field effect transistor; third and fourth insulated gate field effect transistors of said first channel type having source and drain regions of said another conductivity type formed in said second semiconductor substrate and gate electrodes form on said second semiconductor substrate between said source and drain regions of said third and fourth insulated gate field effect transistors; a resistor region of said another conductivity type formed in said second semiconductor substrate and having first and second end portions; first and second power terminals supplied with a power voltage therebetween; means for connecting said gate electrodes of said first and second insulated gate field effect transistors to receive an input signal; means for connecting said drain regions of said first and second insulated gate field effect transistors to produce an output signal; means for connecting said source regions of said third and fourth insulated gate field effect transistors, said second semiconductor substrate and said first power terminal; means for connecting said gate electrode of said third insulated gate field effect transistor, said drain region of said fourth insulated gate field effect transistor and said first end portion of said resistor region; means for connecting said drain region of said third insulated gate field effect transistor, said gate electrode of said fourth insulated gate field effect transistor, said source region of said first insulated gate field effect transistor and said first semiconductor substrate; and means for connecting said source region of said second insulated gate field effect transistor, said well region, said second end of said resistor region, and said second power terminal.

Claim 7

An integrated circuit device comprising: an electrical circuit formed on a first semiconductor substrate with first and second channel type MOS field effect transistors; a power terminal receiving an external power voltage; power control means for controlling power supplied to said electrical circuit from said power terminal, said power control means including: a first MOS field effect transistor having a source connected to said power terminal, a drain and a gate; a second MOS field effect transistor having a source connected to said power terminal, a drain connected to said gate of said first MOS field effect transistor and said electrical circuit, and a gate connected to said drain of said first MOS field effect transistor; and a resistor having one end connected to said drain of said first MOS field effect transistor and said gate of said second MOS field effect transistor; said integrated circuit device comprising a reference voltage terminal connected to other end of said resistor.

Claim 8

An integrated circuit device comprising: an electrical circuit formed on a first semiconductor substrate with first and second channel type MOS field effect transistors; a power terminal receiving an external power voltage; power control means for controlling power supplied to said electrical circuit from said power terminal, said power control means including: a first MOS field effect transistor having a source connected to said power terminal, a drain and a gate; a second MOS field effect transistor having a source connected to said power terminal, a drain connected to said gate of said first MOS field effect transistor and said electrical circuit, and a gate connected to said drain of said first MOS field effect transistor; and a resistor having one end connected to said drain of said first MOS field effect transistor and said gate of said second MOS field effect transistor; said integrated circuit device comprising a reference voltage terminal connected to other end of said resistor.

Claim 9

An integrated circuit device as claimed in claim 5, further comprising a second semiconductor substrate, physically separate from said first semiconductor substrate, wherein said power control means is formed on said second semiconductor substrate.

Claim 10

An integrated circuit device as claimed in claim 6, wherein said resistor has such a value that said second MOS field effect transistors turns off when a current flowing through said electrical circuit is larger than a predetermined value, but turns on otherwise.