Multiple unit adapter

Claim 1

In a multiprocessing digital data processing system having a plurality of high performance storage units, a plurality of instruction processors, each of said instruction processors being individually coupled to each of said high performance storage units, a plurality of input/output processors, each of said input/output processors being individually coupled to each of said high performance storage units and a scientific processor with a repetitive cycling clock means and having a single high performance storage unit port, a multiple unit adapter for coupling the scientific processor to the plurality of high performance storage units, said multiple unit adapter comprising: a single bidirectional scientific process port for coupling said multiple unit adapter to said single high performance storage unit port of the scientific processor; a plurality of bidirectional high performance storage unit ports for individually coupling said multiple unit adapter to the plurality of high performance storage units; a first direction communication means coupled between the single bidirectional scientific processor port and the plurality of bidirectional high performance storage unit ports, said first direction communication means further including a first-in, first-out memory stack means having a plurality of n+1 memory locations for sequentially receiving as many as n successive high performance storage unit requests from said scientific processor during n clock cycles of the repetitive cycling clock means of the scientific processor without receiving an acknowledgement signal from said single bidirectional scientific processor port and further for sequentially receiving a continuous successive string of high performance storage unit requests from said scientific processor during successive clock cycles of the repetitive cycling clock means of the scientific processor so long as an acknowledgement signal is received at least once every n cycles and the high performance storage unit requests are to the same storage unit, to provide a first path for writing information emanating from the single storage unit port of the scientific processor into selected individual high performance storage units of said plurality; and a second direction communication means coupled between the plurality of high performance storage unit ports and the single storage unit port of the scientific processor to provide a second path for returning information read from selected individual high performance storage units of said plurality to the scientific processor via said single storage unit port to thereby provide a digital data processing system capable of storage expansion while maintaining a scientific processor design having a single storage unit port.