US4721871A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High voltage MOS switch circuit with isolation
Assignee: Mitsubishi Electric Corp
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Filing: 1986-10-09
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Granted: 1988-01-26
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Expires: 2006-10-09
Abstract
Abstract A high voltage switch circuit, wherein the source of a first MOS transistor is connected to the gate of a second MOS transistor, the source of the second MOS transistor is connected to the gate of the first MOS transistor, the drain of a third MOS transistor and the gate of a fourth MOS transistor, the drains of the first and fourth MOS transistors are connected to a high voltage input terminal, the sources of the third and fourth MOS transistors are connected to an output terminal, a voltage for turning the transistor ON is applied to the gate of the third MOS transistor, one electrodes of two independent capacitors are connected to the gates of the first and second MOS transistors, and a clock is applied through transmission gates to the other electrode of the two capacitors.
Inventors
- 👤 Akio Kiji
- 👤 Kazuo Aoki
- 👤 Seiichirou Asari
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 05:25
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/10; H03K17/102; H03K17/16; H03K17/161; H03K17/165
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
178 words
A high voltage switch circuit having a plurality of MOS transistors each having a source, a gate and a drain, wherein the source of a first MOS transistor is connected to the gate of a second MOS transistor, the source of the second MOS transistor is connected to the gate of the first MOS transistor, the drain of a third MOS transistor and the gate of a fourth MOS transistor, the drains of the first and fourth MOS transistors are connected to a high voltage input terminal, the sources of the third and fourth MOS transistors are connected to an output terminal, a voltage for turning the third MOS transistor ON is applied to the gate of the third MOS transistor, a first of two electrodes of two independent capacitors are connected to the gates of the first and second MOS transistors, and a clock is applied through transmission gates to the second electrodes of said two capacitors, the transmission gates being selectively enabled or disabled by active or nonactive states of the high voltage switch circuit, respectively.
Claim 2
Dependent Claim
178 words
A high voltage switch circuit having a plurality of MOS transistors each having a source, a gate and a drain, wherein the source of a first MOS transistor is connected to the gate of a second MOS transistor, the source of the second MOS transistor is connected to the gate of the first MOS transistor, the drain of a third MOS transistor and the gate of a fourth MOS transistor, the drains of the first and fourth MOS transistors are connected to a high voltage input terminal, the sources of the third and fourth MOS transistors are connected to an output terminal, a voltage for turning the third MOS transistor ON is applied to the gate of the third MOS transistor, a first of two electrodes of two independent capacitors are connected to the gates of the first and second MOS transistors, and a clock is applied through transmission gates to the second electrodes of said two capacitors, the transmission gates being selectively enabled or disabled by active or nonactive states of the high voltage switch circuit, respectively.
Claim 3
Dependent Claim
34 words
A high voltage switch circuit as set forth in claim 1, wherein a control voltage for setting the high voltage switch circuit to an active or nonactive state is applied to the output terminal.
Claim 4
Dependent Claim
41 words
A high voltage switch circuit as set forth in claim 2, wherein said transmission gate is turned ON when the high voltage switch circuit becomes an active state by the control signal and turned OFF when it becomes a nonactive state.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-01-25 | 1991-07-27 | 1992-01-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-01-25 | 1995-07-27 | 1996-01-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-01-25 | 1999-07-27 | 2000-01-26 | $7700.00 | Window Closed / Lapsed |