Patent US4721867A successfully refreshed from Google Patents.
US4721867A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed logic gate with simulated open collector output
Assignee: Cherry Semiconductor Corp
•
Filing: 1986-04-16
•
Granted: 1988-01-26
•
Expires: 2006-04-16
Abstract
Abstract A high speed logic gate is disclosed in which the voltage across the output transistor is clamped by a diode, a current switch transistor, a resistor connected between the diode and the transistor and a resistor connected to ground. A selectable high impedance is provided to enable the output of the logic gate to simulate an open collector output.
Inventors
- 👤 William E. Headen, Jr.
- 👤 Stephen S. Yole
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 15:19
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/013; H03K19/02; H03K19/08; H03K19/082; H03K19/0823; H03K19/0826
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
270 words
A logic gate comprising: an input for receiving a high or low signal; threshold setting means for determining when the signal from said input has changed; a current switch transistor having a base, a collector and an emitter, the base of said transistor being connected to said threshold setting means; an output transistor having a collector, an emitter connected to ground and a base connected to the emitter of said current switch transistor; a resistor connected between the emitter of said current switch transistor and ground; a diode having an anode and a cathode, the cathode being connected to the collector of said output transistor; a resistor connected between the anode of said diode and the collector of said current switch transistor; a source voltage input for receiving a source voltage; a current limiting resistor connected at one end to the anode of said diode and having an other end; a logic gate output connected to the collector of said output transistor; a second input for receiving a high or low signal; a switching transistor having a collector, an emitter connected to ground and a base connectd to said second input; resistor means for limiting the current through said switching transistor, said resistor means connected between said source voltage and the collector of said switching transistor; a first transistor having a base connected to said resistor means and an emitter connected to said source voltage; and a second transistor having a base connected to the collector of said first transistor, an emitter connected to the other end of said current limiting resistor and a collector connected to said source voltage.
Claim 2
Dependent Claim
270 words
A logic gate comprising: an input for receiving a high or low signal; threshold setting means for determining when the signal from said input has changed; a current switch transistor having a base, a collector and an emitter, the base of said transistor being connected to said threshold setting means; an output transistor having a collector, an emitter connected to ground and a base connected to the emitter of said current switch transistor; a resistor connected between the emitter of said current switch transistor and ground; a diode having an anode and a cathode, the cathode being connected to the collector of said output transistor; a resistor connected between the anode of said diode and the collector of said current switch transistor; a source voltage input for receiving a source voltage; a current limiting resistor connected at one end to the anode of said diode and having an other end; a logic gate output connected to the collector of said output transistor; a second input for receiving a high or low signal; a switching transistor having a collector, an emitter connected to ground and a base connectd to said second input; resistor means for limiting the current through said switching transistor, said resistor means connected between said source voltage and the collector of said switching transistor; a first transistor having a base connected to said resistor means and an emitter connected to said source voltage; and a second transistor having a base connected to the collector of said first transistor, an emitter connected to the other end of said current limiting resistor and a collector connected to said source voltage.
Claim 3
Dependent Claim
30 words
The logic gate of claim 1 wherein said resistor means comprises two resistors connected in series such that the base of said first transistor is connected between said two resistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-01-25 | 1991-07-27 | 1992-01-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-01-25 | 1995-07-27 | 1996-01-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-01-25 | 1999-07-27 | 2000-01-26 | $7700.00 | Window Closed / Lapsed |