Dual fault-masking redundancy logic circuits

Claim 2

An error correcting circuit comprising: at least one pair of interconnections for conveying two respective wire signals, said wire signals intended to both represent a logic input signal, said wire signals being of either a first potential state or a second potential state or a floating logic state, whenever any two interconnections conveying two wire signals being of different potential states are shorted together, said shorted interconnections both then conveying said first potential state; and an input logic circuit for each said pair of interconnections for comparing said wire signal and producing an output signal of: (a) a third logic state if said two wire signals are both of said first potential state, (b) a fourth logic state if said two wire signals are both of said second potential state, said fourth logic state being one of said first and second logic states and complementary to said third logic state, (c) said fourth logic state if said two wire signals are respectively of said first and second potential states, and (d) said third logic state if said two wire signals are respectively of said first and said floating potential states, and (e) said fourth logic state if said two wire signals are respectively of said second and said floating potential states.

Claim 3

A circuit as recited in claim 1, further comprising an output circuit receiving said output signal for producing a buffered signal of either said first potential state or said second potential state on an output line and including means in said output circuit for maintainig said output line in said first potential state if said output line carrying said first potential state is shorted to an output line of another such maintaining means and carrying said second potential state.

Claim 4

A circuit as recited in claim 1, further comprising a logic circuit receiving said output signal and producing two equivalent buffered output signals on two output interconnections, said logic circuit further comprising two output circuits producing said first potential state or said second potential state on each of said output interconnections and including means in said output circuit for maintaining each of said output interconnections in said first potential state if said each output interconnection carrying said first potential state is shorted to an output interconnection of another such output circuit and carrying said second potential state.

Claim 5

A circuit as recited in claim 3, wherein said logic circuit comprises two equivalent logic circuits each having one of said output circuits producing one of said buffered output signals on one of said output interconnections.

Claim 6

An error correcting logic circuit, comprising: a plurality of error correcting input circuits, each input circuit receiving two input interconnections carrying two respective wire signals, intended to both represent an input logic signal of a first logic state or a second logic state, said wire signal being of a first potential state, a second potential state or a floating potential state, said input circuit producing a corrected signal of: (a) a third logic state if said two wire signals are both of said first potential state, (b) a fourth logic state if said two wire signals are both of said second potential state, said fourth logic state being one of said first and second logic states and complementary to said third logic state, (c) said fourth logic state if said two wire signals are respectively of said first and second potential states, and (d) said third logic state if said two wire signals are respectively of said first and said floating potential states, and (e) said fourth logic state if said two wire signals are respectively of said second and said floating potential states; two equivalent logic circuits, each receiving said corrected signals from said plurality of input circuits and producing according to a predetermined logic function on a respective output interconnection an output signal, each said equivalent logic circuit including an output circuit, producing said first potential state or said second potential state on said output interconnection and including means in said output circuit for maintaining each of said output interconnections in said first potential state if said each interconnection carrying said first potential state is shorted to an output interconnection of another such output circuit and carrying said second potential state, the two output interconnections of said two equivalent logic circuits being connected to input interconnections of another said error correcting logic circuit.

Claim 7

An error correcting logic circuit, comprising: a plurality of error correcting input circuits, each input circuit receiving two input interconnections carrying two respective wire signals, intended to both represent an input logic signal of a first logic state or a second logic state, said wire signal being of a first potential state, a second potential state or a floating potential state, said input circuit producing a corrected signal of: (a) a third logic state if said two wire signals are both of said first potential state, (b) a fourth logic state if said two wire signals are both of said second potential state, said fourth logic state being one of said first and second logic states and complementary to said third logic state, (c) said fourth logic state if said two wire signals are respectively of said first and second potential states, and (d) said third logic state if said two wire signals are respectively of said first and said floating potential states, and (e) said fourth logic state if said two wire signals are respectively of said second and said floating potential states; two equivalent logic circuits, each receiving said corrected signals from said plurality of input circuits and producing according to a predetermined logic function on a respective output interconnection an output signal, each said equivalent logic circuit including an output circuit, producing said first potential state or said second potential state on said output interconnection and including means in said output circuit for maintaining each of said output interconnections in said first potential state if said each interconnection carrying said first potential state is shorted to an output interconnection of another such output circuit and carrying said second potential state, the two output interconnections of said two equivalent logic circuits being connected to input interconnections of another said error correcting logic circuit.

Claim 8

An error correcting logic circuit as recited in claim 5, wherein said input circuits include resistive coupling to a voltage source at a potential of said first potential state.

Claim 9

An error correcting logic circuit as recited in claim 6, wherein said output circuits include resistive coupling to a voltage source at a potential of said second potential state.

Claim 10

An error correcting logic circuit as recited in claim 7, wherein said output circuits comprise an emitter-follower circuit.