Ultra high-speed time-to-digital converter

Claim 2

An ultra-high speed time-to-digital converter, comprising: a first input terminal for receiving a start signal; a plurality of gate circuits connected in cascade to form a chain having one end connected to the first input terminal to allow the propagation of the start signal through said chain, all of said gate circuits being constituted by the same integrated circuit devices formed on one and the same semiconductor substrate to show a substantially uniform signal propagation time, and each gate circuit having a signal input, a signal output and a control input, said signal output having a first state when the start signal has propagated through the corresponding gate circuit and a second state different from the first state when the start signal has not propagated through the corresponding gate circuit; a second input terminal for receiving a stop signal; and locking circuit means having an input connected to the second input terminal and a plurality of outputs each connected to the control input of a respective gate circuit of said chain, said locking circuit means acting in response to the reception of a stop signal to lock the gate circuits through which the start signal has not yet propagated, whereby the number of gate circuits gone through by the start signal is a linear function of the time elaspsed between the time when a start signal is received and the time when a stop signal is received.

Claim 3

An ultra-high speed time-to-digital converter, comprising: a first input terminal for receiving a start signal; a plurality of first gate circuits connected in cascade to form a first chain having one end connected to the first input terminal to allow the propagation of the start signal through said first chain, all of the said first gate circuits being constituted by the same integrated circuit devices formed on one and the same semiconductor substrate to shown a substantially uniform first signal propagation time, and each first gate circuit having a signal input and a signal output, the latter having a first state when the start signal has propagated through the corresponding first gate circuit and a second state different from the first state when the start signal has not propagated through the corresponding first gate circuit; a second input terminal for receiving a stop signal; a plurality of second gate circuits connected in cascade to form a second chain having one end connected to the second input terminal to allow the propagation of the stop signal through said second chain, all of said second gate circuits being constituted by the same integrated circuit devices formed on one and the same semiconductor substrate to show a substantially uniform second signal propagation time, and each gate circuit having a signal input and a signal output, the latter having a first state when the stop signal has propagated through the corresponding second gate circuit and a second state different from the first state when the stop signal has not propagated through the corresponding second gate circuit; a plurality of locking circuit means each connected between a respective first gate circuit and a respective corresponding second gate circuit so as to have the state of the signal outputs of all the gate circuits in at least one of said first and second chains locked when the start signal and the stop signal propagating along the parallel paths constituted by said first and second chains simultaneously reach corresponding first and second gate circuits; and coding means connected to the signal outputs of the gate circuits of said at least one chain to provide digital information which is a function of the locked state of said signal outputs.

Claim 4

An ultra-high speed time-to-digital converter, comprising: a first input terminal for receiving a start signal; a plurality of first gate circuits connected in cascade to form a first chain having one end connected to the first input terminal to allow the propagation of the start signal through said first chain, all of the said first gate circuits being constituted by the same integrated circuit devices formed on one and the same semiconductor substrate to shown a substantially uniform first signal propagation time, and each first gate circuit having a signal input and a signal output, the latter having a first state when the start signal has propagated through the corresponding first gate circuit and a second state different from the first state when the start signal has not propagated through the corresponding first gate circuit; a second input terminal for receiving a stop signal; a plurality of second gate circuits connected in cascade to form a second chain having one end connected to the second input terminal to allow the propagation of the stop signal through said second chain, all of said second gate circuits being constituted by the same integrated circuit devices formed on one and the same semiconductor substrate to show a substantially uniform second signal propagation time, and each gate circuit having a signal input and a signal output, the latter having a first state when the stop signal has propagated through the corresponding second gate circuit and a second state different from the first state when the stop signal has not propagated through the corresponding second gate circuit; a plurality of locking circuit means each connected between a respective first gate circuit and a respective corresponding second gate circuit so as to have the state of the signal outputs of all the gate circuits in at least one of said first and second chains locked when the start signal and the stop signal propagating along the parallel paths constituted by said first and second chains simultaneously reach corresponding first and second gate circuits; and coding means connected to the signal outputs of the gate circuits of said at least one chain to provide digital information which is a function of the locked state of said signal outputs.

Claim 5

A converter as claimed in claim 2, wherein said first and second gate circuits are fomed on one and the same semiconductor substrate.

Claim 6

A converter as claimed in claim 2, wherein the directions of propagation of the start signal and of the stop signal along the parallel paths formed by the first and second chains are oppsite to one another.

Claim 7

A converter as claimed in claim 4, wherein each one of said first and second gate circuits has a control input; and each one of said locking circuit means includes a first connecting circuit connecting an output of the corresponding first gate circuit to the control input of the corresponding second gate circuit and a second connecting circuit connecting an output of the corresponding second gate circuit to the control input of the corresponding first gate circuit so as to control the locking of a gate circuit in one chain in response to the change of the signal output of the corresponding gate circuit in the other chain from the first to the second state.

Claim 8

A converter as claimed in claim 2, wherein the directions of propagation of the start signal and of the stop signal along the parallel paths formed by the first and second chains are identical, said first propagation time being longer than said second propagation time.

Claim 9

A converter as claimed in claim 4, wherein each one of said first gate circuits has a control input; and each one of said locking circuit means includes a third gate circuit having a signal input connected to a signal output of the corresponding first gate circuit and a signal output connected to the control input of the corresponding first gate circuit in response to the change of the signal output of the corresponding second gate circuit from the first to the second state only when the signal output of the first gate circuit is still in the first state.

Claim 10

An ultra-high speed time-to-digital converter, comprising: a first input terminal for receiving a start signal; a plurality of gate circuits connected in cascade to form a chain having one end connected to the first input terminal to allow the propagation of the start signal through said chain, all of said gate circuits being constituted by the same integrated circuit devices formed on one and the same semiconductor substrate to shown a substantially uniform signal propagation time, and each gate circuit having a signal input, a signal output and a control input, said signal output having a first state when the start signal has propagated through the corresponding gate circuit and a second state different from the first state when the start signal has not propagated through the corresponding gate circuit; a second input terminal for receiving a stop signal; a plurality of locking circuit means each having a signal input connected to said second input terminal to receive the stop signal and a signal output connected to the control input of the corresponding respective gate circuit, said locking circuit means acting in response to the reception of a stop signal by locking the state of the signal outputs of said gate circuits; and coding means connected to the signal outputs of said gate circuits to provide a digital information which is a function of the locked state of said signal outputs.

Claim 11

An ultra-high speed time-to-digital converter, comprising: a first input terminal for receiving a start signal; a plurality of gate circuits connected in cascade to form a chain having one end connected to the first input terminal to allow the propagation of the start signal through said chain, all of said gate circuits being constituted by the same integrated circuit devices formed on one and the same semiconductor substrate to shown a substantially uniform signal propagation time, and each gate circuit having a signal input, a signal output and a control input, said signal output having a first state when the start signal has propagated through the corresponding gate circuit and a second state different from the first state when the start signal has not propagated through the corresponding gate circuit; a second input terminal for receiving a stop signal; a plurality of locking circuit means each having a signal input connected to said second input terminal to receive the stop signal and a signal output connected to the control input of the corresponding respective gate circuit, said locking circuit means acting in response to the reception of a stop signal by locking the state of the signal outputs of said gate circuits; and coding means connected to the signal outputs of said gate circuits to provide a digital information which is a function of the locked state of said signal outputs.

Claim 12

A converter according to the claim 8, wherein each of said locking circuit means includes gate means having a signal input connected to the second input terminal, a control input connected to a signal output of the corresponding gate circuit and a signal output connected to the control input of the corresponding gate circuit so as to control the locking of the corresponding gate circuit in response to the reception of the stop signal only when the signal output of the corresponding gate circuit is still in the first state.