US4719562A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiprocessor system for intercommunication of processors
Assignee: S A T (societe Anonyme De Telecommunications)
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Filing: 1984-07-18
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Granted: 1988-01-12
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Expires: 2004-07-18
Abstract
Abstract The system according to the invention comprises a central microprocessor and peripheral microprocessors. A direct-access transfer memory is provided for the communication of the processors with one another. The memory is divided into as many distinct, determined zones as there are peripheral processors. The memory is connected to two addressing buses of which the latter serves equally well to address the boxes of the memory by the central microprocessor and to address the zones of the memory allocated to the peripheral microprocessors. The system is particularly well adapted to data transfers between a telephone automatic switch and subscribers' sets.
Inventors
- 👤 Francois P. Bailly
- 👤 Alain Bourgoin
- 👤 Francois Vaillant
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 13:21
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/167
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
299 words
A multiprocessor system comprising: a central processor and n peripheral processors communicating with one another; a transfer memory comprising predetermined distinct zones having unitary elements, each of said zones allocated to and associated with and respectively accessed by its associated peripheral processors; said central processor and said n peripheral processors each comprising means for mastering said transfer memory; means for connecting said central processor to said transfer memory comprising a first addressing bus means and a first multiplexer having an input connected to said first addressing bus means and an output connected to said transfer memory, and a second addressing bus means and a second multiplexer having an input connected to said second addressing bus means and an output connected to said transfer memory, said means for connecting said central processor to said transfer memory comprising further bus means connecting said central processor to another input of said second multiplexer for addressing zones allocated to and associated with said peripheral processors when mastered by said central processor and for connecting said central processor to said peripheral processors; said first and second addressing buses including means for addressing said unitary elements of said transfer memory; said central processor including means for causing one of said pheripheral processors to master said transfer memory and for addressing a zone of said transfer memory associated with said one peripheral processor; means for connecting peripheral processors to another input of said first multiplexer comprising addressing buses α 1 , α 2 . . . α n , respectively, each of n peripheral processors including means for addressing directly said unitary elements of said zone of said memory associated therewith; and means for addressing one of said zones associated with said peripheral processors when a respective one of said peripheral processor masters said transfer memory.
Claim 2
Dependent Claim
299 words
A multiprocessor system comprising: a central processor and n peripheral processors communicating with one another; a transfer memory comprising predetermined distinct zones having unitary elements, each of said zones allocated to and associated with and respectively accessed by its associated peripheral processors; said central processor and said n peripheral processors each comprising means for mastering said transfer memory; means for connecting said central processor to said transfer memory comprising a first addressing bus means and a first multiplexer having an input connected to said first addressing bus means and an output connected to said transfer memory, and a second addressing bus means and a second multiplexer having an input connected to said second addressing bus means and an output connected to said transfer memory, said means for connecting said central processor to said transfer memory comprising further bus means connecting said central processor to another input of said second multiplexer for addressing zones allocated to and associated with said peripheral processors when mastered by said central processor and for connecting said central processor to said peripheral processors; said first and second addressing buses including means for addressing said unitary elements of said transfer memory; said central processor including means for causing one of said pheripheral processors to master said transfer memory and for addressing a zone of said transfer memory associated with said one peripheral processor; means for connecting peripheral processors to another input of said first multiplexer comprising addressing buses α 1 , α 2 . . . α n , respectively, each of n peripheral processors including means for addressing directly said unitary elements of said zone of said memory associated therewith; and means for addressing one of said zones associated with said peripheral processors when a respective one of said peripheral processor masters said transfer memory.
Claim 3
Dependent Claim
24 words
The multiprocessor system of claim 1, wherein said transfer memory has a capacity of 2048 octets and is divided into 16zones of 128 octets.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-01-11 | 1991-07-13 | 1992-01-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-01-11 | 1995-07-13 | 1996-01-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-01-11 | 1999-07-13 | 2000-01-12 | $7700.00 | Window Closed / Lapsed |