Video dot intensity balancer

Claim 2

In a digital video display system wherein information is represented by a series of logic bits in a video stream corresponding to dots to be displayed on a CRT, a video dot intensity balancer comprising means for generating a plurality of logic bits and defining an output on N output lines, wherein N is an integer greater than 1 and a plurality of logic means respectively coupled to said N ouput lines of said bit generating means for comparing adjacent logic bits and outputting an information-defining signal in response thereto, said information-defining signal comprising a plurality of information-defining logic bits, said logic means including an OR gate, one input of which is connected to a first one of said N lines and the other input of which is connected to the ouptut of an AND gate, the inputs of said AND gate connected to a dot stretching enabling line and to an adjacent second of said N lines, the logic bit on said first line being logically ORed with the logic bit on said second adjacent line when there is an enabling signal on said enabling line, whereby each of said information-defining logic bits of a preselected logic value are adjacent at least one bit of identical logic value in said video stream.

Claim 3

The video dot intensity balancer according to claim 1, wherein said logic means defines N outputs, and further comprising an N bit shift register means coupled to said N outputs of said logic means for providing a serial video ouput.

Claim 4

The video dot intensity balancer according to claim 2, wherein said logic means further comprises at least one EXCLUSIVE OR gate having one input coupled to the output of said OR gate and a second input coupled to an inverse enabling line.

Claim 5

The video dot intensity balancer according to claim 1, wherein said logic means operates on said logic bits generated by said bit generating means according to the logic formula: D.sub.k =(DI.sub.k +DI.sub.k+1 ·DSTenb) where k =an integer corresponding to the dots in a display cell of a video display system; D k =The k th bit ouput by said video dot intensity balancer; DI k =the k th bit output by said character generating means; DI k+1 =The bit adjacent the DI k bit and equal to 0 for the first bit output by said bit generating means for a given display cell; DSTenb =a dot stretching enabling logical signal; +=a logical OR operation; and ·=a logical AND operation, to provide said information-defining bits.

Claim 6

In a digital video display system wherein information is represented by a series of logic bits in a video stream corresponding to dots to be displayed on a CRT, a method of dot stretching comprising the steps of: providing a plurality of input logic bits corresponding to information to be displayed on a video screen in a parallel fashion to a logical means; at said logical means, inputting a first logic bit to a first input of a logic AND gate, applying a dot stretching enabling signal to a second input of said logic AND gate, applying the output of said logic AND gate to one input of a logic OR gate, and inputting a second adjacent logic bit to a second input of said logic OR gate, to produce information-defining bits according to the logical formula D k =(DI k +DI k+1 ·DSTenb) where k=an integer corresponding to the dots in a display cell of said video display system; D k =the k th bit output by the logical means; DI k =the k th bit provided to said logic means; DI k+1 =the bit adjacent the DI k bit and equal to 0 for the first input bit of a character cell; DSTenb=a dot stretching enabling logical signal; +=a logical OR operator; ·=a logical AND operator; and outputting said information defining-bits produced by said logical means therefrom in serial fashion.

Claim 7

In a digital video display system wherein information is represented by a series of logic bits in a video stream corresponding to dots to be displayed on a CRT, a method of dot stretching comprising the steps of: providing a plurality of input logic bits corresponding to information to be displayed on a video screen in a parallel fashion to a logical means; at said logical means, inputting a first logic bit to a first input of a logic AND gate, applying a dot stretching enabling signal to a second input of said logic AND gate, applying the output of said logic AND gate to one input of a logic OR gate, and inputting a second adjacent logic bit to a second input of said logic OR gate, to produce information-defining bits according to the logical formula D k =(DI k +DI k+1 ·DSTenb) where k=an integer corresponding to the dots in a display cell of said video display system; D k =the k th bit output by the logical means; DI k =the k th bit provided to said logic means; DI k+1 =the bit adjacent the DI k bit and equal to 0 for the first input bit of a character cell; DSTenb=a dot stretching enabling logical signal; +=a logical OR operator; ·=a logical AND operator; and outputting said information defining-bits produced by said logical means therefrom in serial fashion.

Claim 8

The method according to claim 5, further comprising the step of inverting said information-defining bits.