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US4718977A Expired / Lapsed US ⏱️ 0.0 years remaining

Process for forming semiconductor device having multi-thickness metallization

Assignee: STMicroelectronics SRL
•
Filing: 1985-09-06
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Granted: 1988-01-12
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Expires: 2005-09-06
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Abstract

Abstract Structure and method for metallization patterns of different thicknesses on a semiconductor device or integrated circuit. The improved structure and method utilizes three layers of metal in order to reduce the required number of processing steps. One preferred embodiment entails a single metal deposition sequence followed by two etch steps, while a second embodiment, suitable for thicker metallization, requires only two depositions and two etch steps.

Inventors

  • 👤 Claudio Contiero
  • 👤 Giulio Iannuzzi
  • 👤 Giorgio De Santi
  • 👤 Fabrizio Andreani

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 02:07
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/425

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 177 words
A method of forming an integrated circuit metallization pattern including a first conductor portion having a relatively fine conductor pattern and a second metal portion thicker than said first conductor portion and having a relatively coarse conductor pattern comprising the steps of: depositing an aluminum comprising first metal layer having a first thickness; depositing a titanium comprising second metal layer having a thickness substantially less than said first metal layer on said first metal layer; depositing an aluminum comprising third metal layer having a thickness substantially greater than said first metal layer on said second metal layer; forming a first photoresist mask on said first metal layer; etching said first layer using said first photoresist mask to form said relatively fine conductor pattern; forming a second photoresist mask on said third metal layer; and etching said third metal layer using said second photoresist mask to form said relatively coarse conductor pattern and using only said second metal layer to prevent attack of said first metal layer in said first conductor portion having a relatively fine conductor pattern.
Claim 2
Independent Claim 177 words
A method of forming an integrated circuit metallization pattern including a first conductor portion having a relatively fine conductor pattern and a second metal portion thicker than said first conductor portion and having a relatively coarse conductor pattern comprising the steps of: depositing an aluminum comprising first metal layer having a first thickness; depositing a titanium comprising second metal layer having a thickness substantially less than said first metal layer on said first metal layer; depositing an aluminum comprising third metal layer having a thickness substantially greater than said first metal layer on said second metal layer; forming a first photoresist mask on said first metal layer; etching said first layer using said first photoresist mask to form said relatively fine conductor pattern; forming a second photoresist mask on said third metal layer; and etching said third metal layer using said second photoresist mask to form said relatively coarse conductor pattern and using only said second metal layer to prevent attack of said first metal layer in said first conductor portion having a relatively fine conductor pattern.
Claim 3
Dependent Claim 27 words
The method according to claim 1, where said step of etching said first layer is carried out prior to said second and third metal layer depositing steps.
Claim 4
Dependent Claim 41 words
The method according to claim 1, where said step of etching said first layer is carried out after completely removing said second metal layer over the area to be occupied by said first conductor pattern having a relatively fine conductor pattern.

References Cited (Backward Citations)

US3562604A Cited
US3700510A Cited
US4000842A Cited
JPS52149990A Cited
US4233337A Cited
WO1982001102A1 Cited
US4556897A Cited
US4495026A Cited
US4536951A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1991-01-11 1991-07-13 1992-01-12 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1995-01-11 1995-07-13 1996-01-12 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1999-01-11 1999-07-13 2000-01-12 $7700.00 Window Closed / Lapsed

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