Method and apparatus for exchanging data between data processing units

Claim 2

In interfacing apparatus between first and second data processing units (DPUs), a data exchange device into which the DPUs can read and write data simultaneously for thus exchanging data between said DPUs, such device comprising: (a) first and second random access memories (RAMs), each RAM having a data port and an address port; (b) control logic means for receiving from the first DPU control signals indicative of the operative state of each DPU, said control logic means being responsive to said control signals to generate gate control signals; (c) a first gating means connected to control access by said first DPU to the data and address ports of said first RAM and to control access by said second DPU to the data and address ports of said second RAM, said gating means being responsive to said gate control signals to control such access; (d) a second gating means connected to control access by said first DPU to the data and address ports of said second RAM and to control access by said second DPU to the data and address ports of said first RAM, said gating means being responsive to said gate control signals to control such access; and (e) handshake logic means receiving data from each of said DPUs, which data defines the respective states of said DPUs, for generating commands indicative of said states and providing said commands to the first DPU, said first DPU being responsive thereto to generate said control signals to determine access of said first and second DPUs to said first and second RAMs depending on the operative state of each DPU and thereby allowing one DPU to read and write simultaneously with the other.

Claim 3

The data exchange device of claim 1 wherein said first gating means comprises a first set of gates and said second gating means comprises a second set of gates.

Claim 4

The data exchange device of claim 2 wherein said gate control signals comprise a pair of signals and each gate of said first set of gates is responsive to one of said gate control signals and each gate of said second set of gates is responsive to the other one of said gate control signals.

Claim 5

The data exchange device of claim 3 further including address decoding means receiving memory address signals from each of said DPUs and providing signals in response thereto to said control logic means for determining said gate control signals such that said first and second set of gates allows either DPU access to said first and second RAM only upon receipt of valid memory address signals.

Claim 6

The data exchange device of claim 4 wherein the control logic means is operative to cause the gate control signals to enable either the first set of gates or the second set of gates or to disable both sets of gates.

Claim 7

The data exchange device of claim 5 wherein said control logic means receives a read/write signal from each of said DPUs and is further adapted to direct each read/write signal to said first or second RAM, depending on the access of said DPUs to said RAMs.

Claim 8

The data exchange device of claim 6 wherein each gate of said first and second sets of gates enabling access to the address ports of said RAMs are unidirectional and each gate of said first and second sets of gates enabling access to the data ports of said RAMs are bidirectional.

Claim 9

Apparatus for exchanging information between a programmable controller and a computer, comprising: (a) a microcomputer operative in in accordance with a stored program of instructions to control the exchange of information, said microcomputer receiving information from the programmable controller and the computer for providing memory address and control signals; and (b) a data exchange section having (i) first and second random access memories (RAMs), each RAM having a data port and an address port; (ii) control logic means for receiving from the microcomputer control signals indicative of the operative state of the programmable controller and the computer, said control logic means being responsive to said control signals to generate gate control signals; (iii) a first set of gating means connected to control access by said programmable controller to the data and address ports of said first RAM and to control access by said computer to the data and address ports of said second RAM, each gating means of said first set being responsive to said gate control signals to control such access; (iv) a second set of gating means connected to control access by said programmable controller to the data and address ports of said second RAM and to control access by said computer to the data and address ports of said first RAM, each gating means of said second set being responsive to said gate control signals to control such access; and (v) handshake logic means receiving data from the programmable controller and the computer, which data defines the respective states thereof for generating commands indicative of said states and providing said commands to the microcomputer, said microcomputer being responsive thereto to generate said control signals to determine access of the programmable controller and the computer to said first and second RAMs depending on the operative state of the programmable controller and the computer and thereby allowing the programmable controller and computer to read and write simultaneously.

Claim 10

Apparatus for exchanging information between a programmable controller and a computer, comprising: (a) a microcomputer operative in in accordance with a stored program of instructions to control the exchange of information, said microcomputer receiving information from the programmable controller and the computer for providing memory address and control signals; and (b) a data exchange section having (i) first and second random access memories (RAMs), each RAM having a data port and an address port; (ii) control logic means for receiving from the microcomputer control signals indicative of the operative state of the programmable controller and the computer, said control logic means being responsive to said control signals to generate gate control signals; (iii) a first set of gating means connected to control access by said programmable controller to the data and address ports of said first RAM and to control access by said computer to the data and address ports of said second RAM, each gating means of said first set being responsive to said gate control signals to control such access; (iv) a second set of gating means connected to control access by said programmable controller to the data and address ports of said second RAM and to control access by said computer to the data and address ports of said first RAM, each gating means of said second set being responsive to said gate control signals to control such access; and (v) handshake logic means receiving data from the programmable controller and the computer, which data defines the respective states thereof for generating commands indicative of said states and providing said commands to the microcomputer, said microcomputer being responsive thereto to generate said control signals to determine access of the programmable controller and the computer to said first and second RAMs depending on the operative state of the programmable controller and the computer and thereby allowing the programmable controller and computer to read and write simultaneously.

Claim 11

The apparatus of claim 8 wherein said gate control signals comprise a pair of signals and each gating means of said first set of gating means is responsive to one of said gate control signals and each gating means of said second set of gating means is responsive to the other one of said gate control signals.

Claim 12

The apparatus of claim 9 wherein said data exchange section further includes address decoding means receiving memory address signals from the programmable controller and the computer and providing signals in response thereto to said control logic means for determining said gate control signals such that said first and second set of gating means allow the programmable controller and the computer access to said first and second RAM only upon receipt of valid memory address signals.