US4716578A — Circuit and method for the recovery of data from …

Claim 1

Independent Claim 135 words

An interface circuit for connection between an input data port and a data receiver comprising, a data recovery circuit responsive to a data stream on the input port for generating data pulses corresponding thereto, a clock recovery circuit for deriving clock signals from said data pulses and including inverter means for providing inverted clock signals, circuit means responsive to the clock signals and the data pulses for generating, for each data pulse, a recognition window having a maximum width approximately corresponding to the combined duration of the data pulse being recognized and one of the clock pulses, and a data sycnronization circuit responsive to the output from the circuit means and to the recovered inverted clock signals for providing output data pulses each having a pulse width corresponding to that of a recovered clock cycle.

Claim 2

Dependent Claim 135 words

An interface circuit for connection between an input data port and a data receiver comprising, a data recovery circuit responsive to a data stream on the input port for generating data pulses corresponding thereto, a clock recovery circuit for deriving clock signals from said data pulses and including inverter means for providing inverted clock signals, circuit means responsive to the clock signals and the data pulses for generating, for each data pulse, a recognition window having a maximum width approximately corresponding to the combined duration of the data pulse being recognized and one of the clock pulses, and a data sycnronization circuit responsive to the output from the circuit means and to the recovered inverted clock signals for providing output data pulses each having a pulse width corresponding to that of a recovered clock cycle.

Claim 3

Dependent Claim 87 words

An interface circuit as defined in claim 1 wherein the circuit means comprises a first D-type flip-flop having a preset input terminal and a data input terminal connected to a low-level source, and AND gating means responsive to the coincidence of one of said data pulses, one of the recovered clock signals and the Q output of the first flip-flop for generating a set signal at the preset input terminal, the flip-flop being responsive to the next clocking edge of an inverted clock signal for resetting itself.

Claim 4

Dependent Claim 47 words

An interface circuit as defined in claim 2 wherein the data syncrhonization circuit comprises a second D-type flip-flop having its data input terminal connected to the Q output terminal of the first flip-flop, the second flip-flop being responsive to inverted clock signals for providing said output pulses.

Claim 5

Independent Claim 116 words

A method of recovering data from a data stream received at an input data port, the receiving circuitry comprising a clock recovery circuit for deriving clock and inverted clock signals from a data stream appearing at the input port, and a data synchronization circuit responsive to the recovered inverted clock signals and individual pulses from the data stream for providing output pulses each having a width corresponding to that of a recovered clock cycle, the method comprising the step of, at the input of the synchronization circuit, generating in response to each input data pulse and one of the clock signals a recognition window having a maximum width approximately corresponding to that of a clock cycle.

Claim 6

Independent Claim 116 words

A method of recovering data from a data stream received at an input data port, the receiving circuitry comprising a clock recovery circuit for deriving clock and inverted clock signals from a data stream appearing at the input port, and a data synchronization circuit responsive to the recovered inverted clock signals and individual pulses from the data stream for providing output pulses each having a width corresponding to that of a recovered clock cycle, the method comprising the step of, at the input of the synchronization circuit, generating in response to each input data pulse and one of the clock signals a recognition window having a maximum width approximately corresponding to that of a clock cycle.

Claim 7

Dependent Claim 66 words

A method of recovering data as defined in claim 4 wherein the circuit comprises a first presettable flip-flop and the step of generating the recognition window comprises the steps of momentarily presetting the flip-flop at the coincidence of an input data pulse and one of the recovered clock pulses and resetting the flip-flop by clocking its data input terminal with a subsequent inverted recovered clock signal.

Claim 8

Dependent Claim 62 words

A method of recovering data as defined in claim 5 wherein the coincidence is generated by the ANDing of an input data pulse with one of the recovered clock pulses and with the signal level at one of the output terminals of the first flip-flop thereby generating a presettable signal having a duration approximately corresponding to the switching time of the flip-flop.

Claim 9

Dependent Claim 79 words

A method of recovering data as defined in claim 6 wherein the synchronization circuit comprises a second flip-flop having its data input terminal connected to the other output terminal of said one flip-flop and the method comprising the further step of clocking the second flip-flop with the inverted recovered clock signal thereby providing an output signal at an output terminal of the second flip-flop, the latter output signal having a width corresponding to that of a recovered clock cycle.

Claim 10

Dependent Claim 140 words

An interface circuit for connection between an input data port and a data receiver comprising, a data recovery circuit responsive to a bipolar data stream on the input port for generating a pair of unipolar data streams corresponding thereto, a clock recovery circuit for deriving clock and inverted clock signals from said unipolar data streams, circuit means responsive to the clock signals and to each pulse of the unipolar data streams for generating a recognition window having a maximum width corresponding to the combined duration of one of said pulses and a clock pulse, and a data synchronization circuit responsive to the outputs from the circuit means and to the recovered inverted clock signals for providing a pair of data stream synchronized to the clock signals, each data pulse having a duration corresponding to that of a recovered clock cycle.

Claim 11

Dependent Claim 140 words

An interface circuit for connection between an input data port and a data receiver comprising, a data recovery circuit responsive to a bipolar data stream on the input port for generating a pair of unipolar data streams corresponding thereto, a clock recovery circuit for deriving clock and inverted clock signals from said unipolar data streams, circuit means responsive to the clock signals and to each pulse of the unipolar data streams for generating a recognition window having a maximum width corresponding to the combined duration of one of said pulses and a clock pulse, and a data synchronization circuit responsive to the outputs from the circuit means and to the recovered inverted clock signals for providing a pair of data stream synchronized to the clock signals, each data pulse having a duration corresponding to that of a recovered clock cycle.

Claim 12

Dependent Claim 106 words

An interface circuit as defined in claim 8 wherein the circuit means comprises a first pair of D-type flip-flops each having a preset input terminal and a data input terminal connected to a low-level source, and each flip-flop being associated with an AND gating means responsive to the coincidence of one of the data pulses from a respective one of the unipolar data streams, one of the recovered clock signals and the Q output of its associated flip-flop for generating a set signal at its preset input terminal, the set flip-flop being responsive to the next clocking edge of an inverted clock signal for resetting itself.

Claim 13

Dependent Claim 57 words

An interface circuit as defined in claim 9 wherein the data synchronization circuit comprises a second pair of D-type flip-flops each one having its data input terminal connected to a respective Q output terminal of the first pair of flip-flops, the second pair of flip-flops being responsive to the inverted clock signals for generating said synchronous data.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1990-12-28	1991-06-29	1991-12-29	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1994-12-28	1995-06-29	1995-12-29	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1998-12-28	1999-06-29	1999-12-29	$7700.00	Window Closed / Lapsed

Circuit and method for the recovery of data from a digital data stream

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