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US4715050A
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Digital phase-locked loop circuit
Assignee: Toshiba Corp
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Filing: 1987-03-09
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Granted: 1987-12-22
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Expires: 2007-03-09
Abstract
Abstract During the receipt of a result of comparison from the phase detector representing that the synchronization signal is phase-delayed behind the input signal, the selection circuit sequentially selects the M number of counters, one by one, in a cyclic fashion, in such a direction as to permit the reference clock input to be phase-advanced correspondingly, so that the frequency-divided output signal from the counter to the phase detector can be sequentially phase advanced by 1/M of one cycle of the reference clock. During the receipt of a result of the comparison indicating that the synchronization signal is phase-advanced ahead of the input signal, on the other hand, the selection circuit sequentially selects the M number of counters, one by one, in a cyclic fashion, in such a direction as to allow the reference clock input to be phase-delayed, so that the frequency divided output signal from the counter to the phase detector can be sequentially phase-delayed by 1/M of one cycle of the reference click. When a phase difference occurs between the input signal and the synchronization signal, one cycle time of the synchronization signal is increased or decreased by 1/M of one cycle of the reference clock, thus assuring an enhanced time resolution.
Inventors
- 👤 Koichi Tanaka
- 👤 Satoshi Itoh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 10:10
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099; H03L7/0991; H03L7/0992
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
233 words
A digital phase-locked loop circuit comprising: a reference clock generator for generating an M, where M is an integer of 2 or more, number of reference clock inputs having a frequency substantially the same as N times, where N is an integer, the frequency of an input signal and sequentially phase-shifted by 2π/M radians; an M number of counters for frequency dividing the M number of reference clock inputs, the respective counters being sequentially operated upon receipt of a selection signal and each delivering a first, second and third output signal in a predetermined timing relation; a phase detector for making a phase comparison between the first output signal of a selected one of said M number of counters and said input signal and producing one of a first signal representing a phase delay of said first output signal of said selected counter and a second signal representing a phase advance of said first output signal of said selected counter; and a selection circuit for receiving the signals of said phase detector and the output signals of said M number of counters and sequentially delivering the selection signal in a cyclic fashion in a predetermined direction to said M number of counters to decrease the phase difference between both the signals supplied to said phase detector so that the first output signal of the selected counter is used as a synchronization output signal.
Claim 2
Dependent Claim
233 words
A digital phase-locked loop circuit comprising: a reference clock generator for generating an M, where M is an integer of 2 or more, number of reference clock inputs having a frequency substantially the same as N times, where N is an integer, the frequency of an input signal and sequentially phase-shifted by 2π/M radians; an M number of counters for frequency dividing the M number of reference clock inputs, the respective counters being sequentially operated upon receipt of a selection signal and each delivering a first, second and third output signal in a predetermined timing relation; a phase detector for making a phase comparison between the first output signal of a selected one of said M number of counters and said input signal and producing one of a first signal representing a phase delay of said first output signal of said selected counter and a second signal representing a phase advance of said first output signal of said selected counter; and a selection circuit for receiving the signals of said phase detector and the output signals of said M number of counters and sequentially delivering the selection signal in a cyclic fashion in a predetermined direction to said M number of counters to decrease the phase difference between both the signals supplied to said phase detector so that the first output signal of the selected counter is used as a synchronization output signal.
Claim 3
Dependent Claim
118 words
The digital phase-locked loop circuit according to claim 1, in which said selection circuit is so operated that when it receives both the first signal from said phase detector and a second output signal from a currently-operated counter it selects a counter supplied with a reference clock whose phase is advanced by 2π/M radians ahead that of the reference clock input which is supplied to said currently-operated counter and that when it receives both the second signal from said phase detector and the third output signal from said currently-operated counter it selects a counter supplied with a reference clock whose phase is delayed by 2π/M radians behind the reference clock input which is supplied to said currently-operated counter.
Claim 4
Dependent Claim
99 words
The digital phase-locked loop circuit according to claim 1, in which: said first output signal from the selected counter appears from when a start of a counting operation of the selected counter until the reference clock is counted N/2 times; said second output signal from the selected counter appears from when the reference clock has been counted N times until the selection signal supplied to the selected counter stops; and said third output signal from the selected counter appears from when the reference clock has been counted (N+1) times until the selection signal supplied to the selected counter stops.
Claim 5
Dependent Claim
52 words
The digital phase-locked loop circuit according to claim 1, in which said first signal representing said phase delay of said first output signal of said selected counter is an up-count signal and said second signal representing said phase delay of said first output signal of said selected counter is a down-count signal.
Claim 6
Dependent Claim
44 words
The digital phase-locked loop circuit according to claim 1, in which said predetermined direction is a direction in which said input reference clocks are sequentially phase-advanced with respect to the said counters when said phase comparator delivers the first signal representing said phase delay.
Claim 7
Dependent Claim
42 words
The digital phase locked loop circuit according to claim 1, in which said predetermined direction is a direction in which said input reference clocks are sequentially phase-delayed with respect to said counters when said comparator delivers the second signal representing said phase-advance.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-12-21 | 1991-06-22 | 1991-12-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-12-21 | 1995-06-22 | 1995-12-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-12-21 | 1999-06-22 | 1999-12-22 | $7700.00 | Window Closed / Lapsed |