Method for the simulation of an error in a logic circuit and a circuit arrangement for implementation of the method

Claim 3

The method of claim 1, wherein some of the signals of the input bit pattern are logic signals to be switched through to the bus and others of the signals of the input bit pattern are control signals for the switch elements, and wherein: the step of producing the undefined logic level with the logic circuit model includes ANDing the logic and control signals, for the first simulated switch element, to produce first signals, ORing the AND produced first signals to produce a second signal, inverting the logic signals and ANDing the same with the control signals, for the second simulated switch element, to produce third signals, and ORing the second signals to produce a fourth signal; wherein the steps of imaging the undefined logic level includes applying the second and fourth signals to the first bus model version and logically combining the same to produce a logic output of 0,0,1 for the respective patterns 11,01 and 10 for the second and fourth signals, and applying the second and fourth signals to the second bus model version and logically combining the same to produce a logic output of 1,0,1 for the respective patterns of 11,01 and 10 of the second and fourth signals.

Claim 4

The method of claim 1, wherein some of the signals of the input bit pattern are logic signals to be switched through to the bus and others of the signals of the input bit pattern are control signals for the switch elements, and wherein: the step of producing the undefined logic level with the logic circuit model includes inverting the control signals and ANDing the logic and inverted control signals, for the first simulated switch element, to produce first signals, ORing the AND-produced first signals to produce a second signal, ANDing the inverted control signals with the logic signals, for the second simulated switch element, to produce third signals, and ORing the second signals to produce a fourth signal; wherein the steps of imaging the undefined logic level includes applying the second and fourth signals to the first bus model version and logically combining the same to produce a predetermined logic output for respective predetermined patterns for the second and fourth signals, and applying the second and fourth signals to the second bus model version and logically combining the same to produce predetermined logic output for the same respective predetermined patterns of the second and fourth signals.

Claim 5

The method of claim 1, wherein some of the signals of the input bit pattern are logic signals to be switched through to the bus and others of the signals of the input bit pattern are control signals for the switch elements, and wherein: the step of producing the undefined logic level with the logic circuit model includes inverting the logic signal and ANDing the inverted logic and control signals, for the first simulated switch element, to produce first signals, ORing the AND produced first signals to produce a second signal, ANDing the logic signals with the control signals, for the second simulated switch element, to produce third signals, and ORing the second signals to produce a fourth signal; wherein the steps of imaging the undefined logic level includes applying the second and fourth signals to the first bus model version and logically combining the same to produce a logic output of 0,0,1 for the respective patterns 11,02 and 10 for the second and fourth signals, and applying the second and fourth signals to the second bus model version and logically combining the same to produce a logic output of 1,0,1 for the respective patterns of 11,01 and 10 of the second and fourth signals.

Claim 8

A simulation circuit arrangement for simulating an error in a logic circuit which is designed to optionally connect two logic levels to a bus via an input circuit, comprising switch elements connected to the bus, for receiving input bit patterns including control signals and logic signals to be switched through to the bus, said simulation circuit arrangement comprising: a simulation model including an input circuit simulation model and a bus circuit simulation model connected to said input circuit simulation model; said input circuit simulation model including an input for receiving the input bit pattern, and an output, and operable in response to the input bit pattern to produce an undefined logic level at said output; and said bus circuit simulation model including an input connected to said output of said input circuit simulation model, and an output, and operable to image the undefined logic level to a defined logic level at its output.

Claim 9

A simulation circuit arrangement for simulating an error in a logic circuit which is designed to optionally connect two logic levels to a bus via an input circuit, comprising switch elements connected to the bus, for receiving input bit patterns including control signals and logic signals to be switched through to the bus, said simulation circuit arrangement comprising: a simulation model including an input circuit simulation model and a bus circuit simulation model connected to said input circuit simulation model; said input circuit simulation model including an input for receiving the input bit pattern, and an output, and operable in response to the input bit pattern to produce an undefined logic level at said output; and said bus circuit simulation model including an input connected to said output of said input circuit simulation model, and an output, and operable to image the undefined logic level to a defined logic level at its output.

Claim 10

The simulation circuit arrangement of claim 6, wherein, for simulation of each switch element, said input circuit simulation model comprises: first and second AND gates each including an input for receiving a respective logic signal, an input for receiving a respective control signal and an output; first and second OR gates each including an input respectively connected to said outputs of said AND gates, and an output connected to said bus circuit simulation model; and an inverter connected to the logic signal input of said second AND gate for inverting the respective logic signal.

Claim 11

The simulation circuit arrangement of claim 6, wherein for each switch element of the simulated circuit which is to connect its logic signal to the bus in inverted form, said input circuit simulation model comprises:

Claim 12

first and second AND gates each including an input for receiving a respective logic signal, an input for receiving a respective control signal, and an output;

Claim 13

first and second AND gates each including an input for receiving a respective logic signal, an input for receiving a respective control signal, and an output;

Claim 14

first and second inverters connected to the respective logic signal inputs of said first and second AND gates to receive and invert the respective logic signals; first and second OR gates each including an input connected to the respective outputs of said first and second AND gates, and an output connected to said bus circuit simulation model.

Claim 15

first and second inverters connected to the respective logic signal inputs of said first and second AND gates to receive and invert the respective logic signals; first and second OR gates each including an input connected to the respective outputs of said first and second AND gates, and an output connected to said bus circuit simulation model.

Claim 16

The simulation circuit arrangement of claim 6, wherein for each switch element of the simulated circuit which is to connect a first logic level in response to receipt of a second logic level, said input circuit simulation model comprises: inverter means connected to receive and invert respective signals of the input bit pattern.

Claim 17

The simulation circuit arrangement of claim 6, wherein, for each switch element of the simulated circuit which has a logic signal input and two separate selection inputs which receive mutually inverse control signals, said input circuit simulation model comprises: a first inverter connected to receive one of the control signals; a first OR gate including a first input for receiving the other control signal, a second input connected to said inverter; a second inverter connected to receive the logic signal; first and second AND gates each including a first input, a second input and an output, said first inputs connected to said output of said OR gate, said second input of said first AND gate connected to receive the logic signal, and said second input of said second AND gate connected to said second inverter; and third and fourth OR gates each including an input respectively connected to said outputs of said first and second AND gates, and an output connected to said bus circuit simulation model.

Claim 18

The simulation circuit arrangement of claim 6, wherein each switch element of the simulated circuit which is composed of a series connection of two p-channel field effect transistors and two n-channel field effect transistors between a supply potential and a reference potential, and in which the gates of the intermediate p-channel and n-channel transistors of the series are commonly connected to receive the logic signal and their commonly connected source-drain connection serves as an output to the bus, and in which gates of the remaining p-channel and n-channel transistors respectively receive control signals, said input circuit simulation model comprises: a first inverter connected to receive one of the control signals; a second inverter connected to receive the logic signal; first and second AND gates each including first and second inputs and an output; said first and second inputs of said first AND gate respectively connected to said first and second inverters; said first input of said second AND gate connected to receive the other of the control signals; said second input of said second AND gate connected to receive the logic signal; and first and second OR gates each including an input respectively connected to said outputs of said AND gates and an output connected to said bus circuit simulation model.

Claim 19

The simulation circuit arrangement of claim 6, wherein said bus circuit simulation model comprises: first and second NOR gates each including first and second inputs, and an output; said first input of each of said NOR gates cross-coupled to the respective output of the other NOR gate; and said second inputs connected to said input circuit simulation model.

Claim 20

The simulation circuit arrangement of claim 6, wherein said bus circuit simulation model comprises: an AND gate including an inverting input and a non-inverting input each connected to said input circuit simulation model, and an output.

Claim 21

The simulation circuit of claim 6, wherein said bus circuit simulation model comprises: a first input connected to said input circuit simulation model to operate in a no-load situation; a second input; an output; and an inverter connected between said second input and said output.

Claim 22

The simulation circuit of claim 6, wherein said bus circuit simulation model comprises: first and second NOR gates each including first and second inputs and an output; said first inputs connected to said input circuit simulation model, and said second inputs cross-connected to the opposite respective outputs; and an inverter connected to the output of said first NOR gate to form the output of said bus circuit simulation model.

Claim 23

The simulation circuit of claim 6, wherein said bus circuit simulation model comprises: a first input and an output directly connected together and to said input circuit simulation model; and a second input connected to said input circuit simulation model and operated in a no-load condition.

Claim 24

The simulation circuit of claim 6, wherein said bus circuit simulation model comprises: a NAND gate including an inverting input connected to said input circuit simulation model; a non-inverting input connected to said input circuit simulation model; and an output providing the imaged signal.