Instruction prefetch buffer control

Claim 3

The method recited in claim 1 wherein the instruction prefetch buffer stores instructions of variable lengths, said method further comprising the step of determining the length of an instruction read out of the buffer and incrementing the instruction execution buffer according to the length of the instruction if the instruction is not a branch or jump instruction.

Claim 4

The method recited in claim 2 further comprising the steps of: setting the instruction fetch pointer and the instruction execution pointer to zero if the instruction read out of the buffer is a branch or jump instruction and the target instruction is not within said range; and reading the next instruction from a main memory storing instructions to a location in said buffer pointed to by said fetch pointer.

Claim 5

The method recited in claim 3 further comprising the steps of: testing for the condition of equality of the instruction fetch pointer and the instruction execution pointer as an indication that the buffer is empty; and reading a next instruction from said main memory if the buffer is empty.

Claim 6

An instruction prefetch buffer control for buffer means that stores the code for a number of instructions that have already been executed as well as the code for a number of instructions yet to be executed, said instruction prefetch buffer control comprising: first register means for storing an instruction fetch pointer, said instruction fetch pointer being supplied to said buffer means by said first register means as a write pointer which points to the location where a new word is to be written into said buffer means; second register means for storing an instruction execution pointer, said instruction execution pointer being supplied to said buffer means by said second register means as a read pointer which points to the location in said buffer means where a word is to be read from said buffer means; decoding means for decoding an instruction read from said buffer means to determine if that instruction is a branch or jump instruction; first adder means for incrementing said first register means to increment said instruction fetch pointer for sequential instructions, said first adder means calculating a new instruction fetch pointer for branch or jump instructions; second adder means for incrementing said second register means to increment said instruction execution pointer for sequential instructions, said second adder means calculating a new instruction execution pointer for branch or jump instructions; first logic means responsive to said decoding means for determining if a target instruction of a branch or jump instruction read from said buffer means is within a range of instructions which may be in said buffer means; and second logic means for determining if a target instruction found to be within said range is in said buffer means, said second logic means including third adder means responsive to said first adder an a branch target address to calculate whether the target instruction is contained in said buffer means and, if it is, causing the new instruction execution pointer calculated by said second adder means to be loaded into said second register means.

Claim 7

An instruction prefetch buffer control for buffer means that stores the code for a number of instructions that have already been executed as well as the code for a number of instructions yet to be executed, said instruction prefetch buffer control comprising: first register means for storing an instruction fetch pointer, said instruction fetch pointer being supplied to said buffer means by said first register means as a write pointer which points to the location where a new word is to be written into said buffer means; second register means for storing an instruction execution pointer, said instruction execution pointer being supplied to said buffer means by said second register means as a read pointer which points to the location in said buffer means where a word is to be read from said buffer means; decoding means for decoding an instruction read from said buffer means to determine if that instruction is a branch or jump instruction; first adder means for incrementing said first register means to increment said instruction fetch pointer for sequential instructions, said first adder means calculating a new instruction fetch pointer for branch or jump instructions; second adder means for incrementing said second register means to increment said instruction execution pointer for sequential instructions, said second adder means calculating a new instruction execution pointer for branch or jump instructions; first logic means responsive to said decoding means for determining if a target instruction of a branch or jump instruction read from said buffer means is within a range of instructions which may be in said buffer means; and second logic means for determining if a target instruction found to be within said range is in said buffer means, said second logic means including third adder means responsive to said first adder an a branch target address to calculate whether the target instruction is contained in said buffer means and, if it is, causing the new instruction execution pointer calculated by said second adder means to be loaded into said second register means.

Claim 8

The instruction prefetch buffer control recited in claim 5 wherein said buffer means stores instructions of variable length, further comprising length means for determining the length of an instruction read out of said buffer means, said second adder means being responsive to said length determining means for incrementing said instruction execution pointer according to the length of the instruction read out of said buffer means.

Claim 9

The instruction prefetch buffer control recited in claim 6 further comprising means responsive to said first and second logic means for setting said first and second registers to zero if the target instruction is not within said range or, if within said range, not in said fuffer means, whereby said fetch pointer pointer to an initial location in said buffer means where a new word is to be written into said buffer means.

Claim 10

The instruction prefetch buffer control recited in claim 7, further comprising comparing means connected to said first and second register means for determining the condition of equality of the instruction fetch pointer and the instruction execution pointer as an indication that said buffer means is empty, said comparing means causing an instruction to be read from a main memory storing instructions.