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US4714948A Expired / Lapsed US ⏱️ 0.0 years remaining

HEMT with epitaxial narrow bandgap source/drain contacts isolated from wide bandgap layer

Assignee: Fujitsu Ltd
•
Filing: 1986-03-13
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Granted: 1987-12-22
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Expires: 2006-03-13
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Abstract

Abstract The present invention is related to an improvement of a high-electron mobility transistor (HEMT) which has an undoped GaAs layer and an N-doped AlGaAs layer a heterojunction formed between the undoped GaAs layer and the N-doped AlGaAs layer, respectively a gate electrode on the N-doped AlGaAs layer, and an electron-storing layer formed in proximity to the heterojunction due to the difference in electron affinity between the undoped GaAs layer and the N-doped AlGaAs layer. The known HEMT has a disadvantage in that during the formation of the source and drain regions by means of, for example, thermal diffusion, the impurities of the N-doped AlGaAs layer may diffuse into the undoped GaAs layer through the heterojunction so that the mobility of the electrons in the electron-storing layer is lessened. This disadvantage is removed in the present invention by the provision of a conduction layer formed by the epitaxial growth of highly-doped GaAs. The known HEMT also has a disadvantage in that the source electrode or the drain electrode is electrically connected to the N-doped AlGaAs layer so that the electrons in this layer may lessen the mobility. This disadvantage is also eliminated in the present invention by the provision of an insulating layer. The heterojunction may be formed between Gallium Aluminum Arsenide and Gallium Arsenide, Gallium Aluminum Arsenide and Germanium, Gallium Arsenide and Germanium, Cadmium Telluride and Indium Antimonide, or Gallium Antimonide and Indium Arsenide.

Inventors

  • 👤 Takashi Mimura
  • 👤 Satoshi Hiyamizu

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 23:46
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/113; H10D62/115; H10D62/116; H10D30/00; H10D30/40; H10D30/47; H10D30/471; H10D30/472; H10D30/475; H10D30/4755; H10D30/80

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 225 words
A semiconductor device comprising: a first single crystalline semiconductor layer; a second single crystalline semiconductor layer doped with N-type impurities, having an electron affinity less than that of said first single crystalline semiconductor layer, a heterojunction being formed between said first and second single crystalline semiconductor layers; a gate electrode formed on said second single crystalline semiconductor layer; an electron-storing layer for storing electrons and acting as a conduction channel, formed adjacent to said heterojunction and within said first single crystalline semiconductor layer, due to the difference in electron affinity between said first and second single crystalline semiconductor layers; a pair of conduction layers comprising substantially the same semiconductor material as said first single crystalline semiconductor layer, being highly doped with N-type impurities, and extending through said second single crystalline semiconductor layer into said first single crystalline semiconductor layer to a depth level with the depth of said heterojunction and forming an epitaxial connection with said first single crystalline semiconductor layer; an insulating layer, interposed between said conduction layers and said second single crystalline semiconductor layer, composed of oxide or nitride of said second single crystalline semiconductor layer; and a pair of electrodes, respectively, formed on said pair of conduction layers and electrically connected to said conduction channel via said conduction layer, said pair of electrodes electrically connected to each other through said conduction channel.
Claim 2
Dependent Claim 225 words
A semiconductor device comprising: a first single crystalline semiconductor layer; a second single crystalline semiconductor layer doped with N-type impurities, having an electron affinity less than that of said first single crystalline semiconductor layer, a heterojunction being formed between said first and second single crystalline semiconductor layers; a gate electrode formed on said second single crystalline semiconductor layer; an electron-storing layer for storing electrons and acting as a conduction channel, formed adjacent to said heterojunction and within said first single crystalline semiconductor layer, due to the difference in electron affinity between said first and second single crystalline semiconductor layers; a pair of conduction layers comprising substantially the same semiconductor material as said first single crystalline semiconductor layer, being highly doped with N-type impurities, and extending through said second single crystalline semiconductor layer into said first single crystalline semiconductor layer to a depth level with the depth of said heterojunction and forming an epitaxial connection with said first single crystalline semiconductor layer; an insulating layer, interposed between said conduction layers and said second single crystalline semiconductor layer, composed of oxide or nitride of said second single crystalline semiconductor layer; and a pair of electrodes, respectively, formed on said pair of conduction layers and electrically connected to said conduction channel via said conduction layer, said pair of electrodes electrically connected to each other through said conduction channel.
Claim 3
Dependent Claim 25 words
A semiconductor device according to claim 1, wherein said first single crystalline semiconductor layer comprises GaAs and said second single crystalline semiconductor layer comprises AlGaAs.
Claim 4
Dependent Claim 23 words
A semiconductor device according to claim 1, wherein said conduction layers comprise one member selected from the group consisting of GaAs and Ge.
Claim 5
Dependent Claim 17 words
A semiconductor device according to claim 1, wherein said insulating layer comprises aluminum oxide or aluminum nitride.

References Cited (Backward Citations)

US3681668A Cited
US3956033A Cited
US4163237A Cited
US4291327A Cited
US4424525A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1990-12-21 1991-06-22 1991-12-22 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1994-12-21 1995-06-22 1995-12-22 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1998-12-21 1999-06-22 1999-12-22 $7700.00 Window Closed / Lapsed

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