Three-voltage level detector for indicating a high level, mid-level or low level voltage

Claim 1

A three-voltage level detector comprising: input means for receiving at an input terminal of the detector an input logic signal having either a high level, mid-level or low level voltage; first level sensing buffer means responsive to said input logic signal for generating a first output sense voltage indicative of whether said input logic signal is either at the (a) high level voltage or (b) mid-level or low level voltage; said first sensing means including a differential amplifier formed of first and second bipolar transistors having their emitters coupled together, said first transistor defining an input transistor and having its base coupled to said input logic signal, said second transistor defining a reference transistor and having its base coupled to a first sensing voltage; second level sensing means responsive to said input logic signal for generating a second output sense voltage indicative of whether said input logic signal is either at the (a) high level or mid-level voltage or (b) low level voltage; first logic means responsive to said first and second output sense voltages for generating at a first output terminal of the detector a first output signal being in a high level only when said input logic level is at the high level voltage; second logic means responsive to said first and second output sense voltages for generating at a second output terminal of the detector a second output signal being in a high level only when said input logic level is at the low level voltage; and third logic means responsive to said first and second output sense voltages for generating at a third output terminal of the detector a third output signal being in a high level only when said input logic level is at the mid-level voltage.