Dual layer encapsulation coating for III-V semiconductor compounds

Claim 2

A process for providing a mask or encapsulation coating over the exterior surface of a III-V compound semiconductor, said process comprising the steps of: depositing a layer of silicon to a select thickness over the exterior surface of the III-V compound semiconductor utilizing a deposition temperature not to exceed the congruent evaporation temperature of the III-V compound semiconductor; and depositing a layer of silicon nitride to a select thickness over the exterior surface of the silicon layer.

Claim 3

The process of claim 1 wherein said silicon is deposited by electron beam evaporation and said silicon nitride is deposited by plasma enhanced chemical vapor deposition.

Claim 4

The process of claim 2 wherein said silicon is deposited to a thickness within the range of 150 angstroms to 5000 angstroms.

Claim 5

The process of claim 3 wherein said silicon is electron beam evaporated at a rate of 6 to 8 angstroms per second and said III-V compound semiconductor is heated to a temperature in the range of 150° C. to 300° C. during said electron beam evaporation of said silicon.

Claim 6

The process of claim 4 wherein said silicon is electron beam evaporated at a pressure of approximately 1.2 microtorr.

Claim 7

The process of claim 2 wherein said silicon nitride is deposited to a thickness within the range of 150 angstroms to 5000 angstroms.

Claim 8

The process of claim 6 wherein said silicon nitride is deposited by introducing: ammonia gas at a flow rate of approximately 5 standard cubic centimeters per minute, silane gas at a flow rate of approximately 390 standard cubic centimeters per minute, and nitrogen gas at a flow rate of 700 standard cubic centimeters per minute.

Claim 9

The process of claim 7 wherein said silicon nitride is deposited at a pressure of approximately 650 millitorr.

Claim 10

The process of claim 6 wherein said silicon nitride is deposited between an upper electrode maintained at a temperature of approximately 60° C. and a lower electrode maintained at a temperature of approximately 220° C. at a radio frequency power of 10 watts.

Claim 11

A process for providing a metallized contact to a III-V compound semiconductor of the type having an encapsulation coating thereon consisting of a layer of silicon deposited on the III-V compound semiconductor at a deposition temperature not exceeding the congruent evaporation temperature of the III-V compound semiconductor, said silicon layer, in turn, being overlayed with a layer of silicon nitride, said process comprising: defining select areas to etch on the outside surface of the silicon nitride layer by masking those areas on the outside surface of the silicon nitride layer not to be etched; reactive ion etching the silicon nitride layer in the areas selectively defined for etching; plasma etching the silicon layer in the areas selectively defined for etching; electron beam evaporation titanium and gold in sequence to overlay the select areas of the III-V compound exposed by said etching; and heating said titanium and gold to provide an alloy of titanium and gold.

Claim 12

A process for providing a metallized contact to a III-V compound semiconductor of the type having an encapsulation coating thereon consisting of a layer of silicon deposited on the III-V compound semiconductor at a deposition temperature not exceeding the congruent evaporation temperature of the III-V compound semiconductor, said silicon layer, in turn, being overlayed with a layer of silicon nitride, said process comprising: defining select areas to etch on the outside surface of the silicon nitride layer by masking those areas on the outside surface of the silicon nitride layer not to be etched; reactive ion etching the silicon nitride layer in the areas selectively defined for etching; plasma etching the silicon layer in the areas selectively defined for etching; electron beam evaporation titanium and gold in sequence to overlay the select areas of the III-V compound exposed by said etching; and heating said titanium and gold to provide an alloy of titanium and gold.

Claim 13

The process of claim 10 wherein said plasma etching is conducted in an atmosphere of oxygen and carbontetrafluoride maintained at a pressure of approximately 350 millitorr and utilizing a radio frequency power of approximately 150 watts.

Claim 14

The process of claim 11 wherein said oxygen is introduced at a flow rate of approximately 2 standard cubic centimeters and said carbontetrafluoride is introduced at a flow rate of approximately 40 standard cubic centimeters during said plasma etching process.

Claim 15

The process of claim 10 wherein said reactive ion etching is conducted in an atmosphere of oxygen and carbontetrafluoride maintained at a pressure of approximately 20 millitorr and utilizing a radio frequency power of approximately 50 watts.

Claim 16

The process of claim 13 wherein said oxygen is introduced at a flow rate of approximately 5 standard cubic centimeters and said carbontetrafluoride is introduced at a flow rate of approximately 20 standard cubic centimeters during said reactive ion etching process.

Claim 17

The process of claim 10 wherein said titanium is evaporated at a rate of approximately 5 angstroms per second under a pressure of approximately 1.2 microtorr to a thickness in the range of 150 angstroms to 1,000 angstroms.

Claim 18

The process of claim 10 wherein said gold is evaporated at a rate of approximately 10 angstroms per second under a pressure less than 1.2 microtorr to a thickness in the range of 1.5 K angstroms to 10 K angstroms.

Claim 19

The process of claim 10 wherein said heating of said titanium and gold to provide said titanium gold alloy occurs in a temperature range of 300° C. to 700° C. for a time duration in the range of 15 seconds to 60 seconds.