CMOS subtractor

Claim 1

In a digital computer wherein the difference between two N-bit binary numbers is to be calculated, N stages of cascaded binary adders to effect subtraction by utilizing two's complement arithmetic, starting from the least significant bits in the two N-bit binary numbers, each one of the N stages being fabricated in CMOS circuitry to accept corresponding bits A i , B i , and a borrow-in signal, X i , and to produce a difference signal, D i , and a carry-out signal, X i+1 , each one of the N stages comprising: (a) a first and a second inverter, responsive respectivey to the A i and B i bits to product A i and B i signals; (b) a first transmission gate conditioned to pass the A i bit when the B i bit is at a logic zero level and the B i signal is at a logic one level; (c) a second transmission gate conditioned to pass the A i signal when the B i bit is at a logic one level and the B i signal is at a logic zero level; (d) OR gate means, responsive to the outputs of the first and the second transmission gates, for producing a signal P corresponding to the one of the first and second transmission gates conditioned to pass a signal; (e) a third inverter, responsibe to the signal P, for producing a signal P; (f) a fourth inverter, responsibe to the borrow-in bit X i , for producing a signal X i ; (g) third and fourth transmission gates, conditioned by the signal P and to the signal P to pass either the borrow-in bit X i or the signal X i ; and (h) borrow-out generating means, responsive to the carry-in signal, X i , the P signal, the P signal, the bit A i and the output B i of the second inverter, to produce a borrow-out signal described by the Boolean expression, [(A i +B i )X i +A i B i ], the borrow-out generating means consisting of: (i) a pair of p-channel FETS and a pair of n-channel FETS connected serially between a voltage source and ground and controlled by the bit A i and the output B i of the second inverter to produce the carry-out signal X i+1 when the logic level of the bits A i , B i differ, the pair of p-channel FETS being conductive when A i =0 and B i =1 to produce X i+1 =1 and the pair of n-channel FETS being conductive when A i =1 and B i =0 to produce X i+1 =0; and (ii) a fifth transmission gate, conditioned by the P and P signals to produce X i+1 =X i when A i =B i .