AM stereo receiver

Claim 2

An AM stereo receiver for receiving AM stereo signals containing ID signals which represent different AM stereo systems, said AM stereo receiver comprising: an IF circuit for generating an IF signal based on a received signal; a PLL circuit for locking onto the frequency of said IF signal; a clock circuit for generating a clock signal based on a signal obtained from said PLL circuit; ID signal detector means responsive to a signal from said PLL circuit for detecting any one of said ID signals and for producing a detected ID signal; pulse generator means for generating a first pulse signal having a pulse width corresponding to a plurality of cycles of the detected ID signal; counter means for counting the number of said clock pulses occurring during when said first pulse signal is present; and distinguishing means for distinguishing each detected ID signal from a number of different ID signals based on the counted result of said counter means, thereby making it possible to distinguish one ID signal from a number of different ID signals with the use of a single circuit path.

Claim 3

An AM stereo receiver as claimed in claim 1, wherein said ID signal detector means comprises a quadrature detector which receives said IF signal.

Claim 4

An AM stereo receiver as claimed in claim 1 wherein said ID signal detector means comprises said phase comparator.

Claim 5

An AM stereo receiver for receiving AM stereo signals containing ID signals which represent different AM stereo systems, said AM stereo receiver comprising: an IF circuit for generating an IF signal based on a received signal; a PLL circuit for locking onto the frequency of said IF signal; a clock circuit for generating a clock signal based on a signal obtained from said PLL circuit; ID signal detector means responsive to a signal from said PLL circuit for detecting any one of said ID signals and for producing a detected ID signal; pulse generator means for generating a first pulse signal having a pulse width corresponding to a plurality of cycles of the detected ID signal; counter means for counting the number of said clock pulses occurring during when said first pulse signal is present; and distinguishing means for distinguishing each detected ID signal from a number of different ID signals based on the counted result of said counter means, thereby making it possible to distinguish one ID signal from a number of different ID signals with the use of a single circuit path, wherein said counter means comprises an AND gate for receiving said clock pulses and said first pulse signal and a plurality of flip flops connected to an output of said AND gate in cascade, said flip flops producing a signal representing the counted number of said clock pulses, wherein said distinguishing means comprises a logic circuit which receives output signals from said flip flops to detect one of a plurality of ranges in which the counted number of said clock pulses falls, wherein said distinguishing means further comprises first latch means for storing the output signal of said logic circuit after the presence of each first pulse signal and wherein said distinguishing means further comprises second latch means connected to said first latch means for storing the output signal of said first latch means, and OR gate means for taking a logic OR between the output signals of said first and second latch means.

Claim 6

An AM stereo receiver for receiving AM stereo signals containing ID signals which represent different AM stereo systems, said AM stereo receiver comprising: an IF circuit for generating an IF signal based on a received signal; a PLL circuit for locking onto the frequency of said IF signal; a clock circuit for generating a clock signal based on a signal obtained from said PLL circuit; ID signal detector means responsive to a signal from said PLL circuit for detecting any one of said ID signals and for producing a detected ID signal; pulse generator means for generating a first pulse signal having a pulse width corresponding to a plurality of cycles of the detected ID signal; counter means for counting the number of said clock pulses occurring during when said first pulse signal is present; and distinguishing means for distinguishing each detected ID signal from a number of different ID signals based on the counted result of said counter means, thereby making it possible to distinguish one ID signal from a number of different ID signals with the use of a single circuit path, wherein said counter means comprises an AND gate for receiving said clock pulses and said first pulse signal and a plurality of flip flops connected to an output of said AND gate in cascade, said flip flops producing a signal representing the counted number of said clock pulses, wherein said distinguishing means comprises a logic circuit which receives output signals from said flip flops to detect one of a plurality of ranges in which the counted number of said clock pulses falls, wherein said distinguishing means further comprises first latch means for storing the output signal of said logic circuit after the presence of each first pulse signal and wherein said distinguishing means further comprises second latch means connected to said first latch means for storing the output signal of said first latch means, and OR gate means for taking a logic OR between the output signals of said first and second latch means.

Claim 7

An AM stereo receiver applicable to receive AM stereo signals containing ID signals which represent different AM stereo systems, said AM stereo receiver comprising: ID signal detector means for detecting any one of said ID signals and for producing a detected ID signal; distinguishing means for distinguishing each detected ID signal from a number of different ID signals and for producing an indication signal along a plurality of channels representing different AM stereo system; first latch means connected to said distinguishing means through said plurality of channels for storing the distinguished result; second latch means connected to said first latch means through said plurality of channels for storing the output of said first latch means such that said first latch means stores the present distinguished result and said second latch means stores the previous distinguished result; logic gate means connected to said first and second latch means through said plurality of channels for producing said indication signal when said indication signal is present at least in one of said first and second latch means.

Claim 8

An AM stereo receiver applicable to receive AM stereo signals containing ID signals which represent different AM stereo systems, said AM stereo receiver comprising: ID signal detector means for detecting any one of said ID signals and for producing a detected ID signal; distinguishing means for distinguishing each detected ID signal from a number of different ID signals and for producing an indication signal along a plurality of channels representing different AM stereo system; first latch means connected to said distinguishing means through said plurality of channels for storing the distinguished result; second latch means connected to said first latch means through said plurality of channels for storing the output of said first latch means such that said first latch means stores the present distinguished result and said second latch means stores the previous distinguished result; logic gate means connected to said first and second latch means through said plurality of channels for producing said indication signal when said indication signal is present at least in one of said first and second latch means.

Claim 9

An AM stereo receiver as claimed in claim 5, wherein said first latch means comprises a plurality of shift registers inserted in said plurality of channels, respectively.

Claim 10

An AM stereo receiver as claimed in claim 6, wherein said second latch means comprises a plurality of shift registers inserted in said plurality of channels, respectively.

Claim 11

An AM stereo receiver as claimed in claim 7, wherein said logic gate means comprises a plurality of OR gates inserted in said plurality of channels, respectively, so as to receive an output of said shift register in said first latch means and an output of said shift register in said second latch means.

Claim 12

An AM stereo receiver as claimed in claim 8, wherein outputs of said plurality of OR gates are connected to a cutting means to cut off the output from said OR gates when more than one channel carries said indication signal.