Separating circuit of luminance and chrominance signals for TV receiver selecting between three three line comb filters

Claim 2

A circuit having comb filters for separating a luminance signal or a chrominance signal from a composite signal of TV signals in the NTSC system comprising: (a) signal delay means including first, second, third, and fourth line memory units each being sequentially connected in series, a delay time of each said line memory unit being identical to a horizontal scanning period, and said first line memory unit being connected to an input terminal to which the composite signal is supplied; (b) a first comb filter including: a first weighting circuit connected to said input terminal for receiving the composite video signal from said input terminal and for weighting the composite video signal; a second weighting circuit connected to said first line memory unit for receiving a first delay signal therefrom and for weighting said first delay signal; a third weighting circuit connected to said second line memory unit for receiving a second delay signal therefrom and for weighting said second delay signal; and a first adder circuit connected to said first, second, and third weighting circuits for adding said weighted composite signal and said weighted first and second delay signals, said first comb filter forming a comb filter together with said first and second line memory units of said signal delay means for generating a first chrominance signal; (c) a second comb filter comprising; a fourth weighting circuit connected to said first line memory unit for receiving a first delay signal therefrom and for weighting said first delay signal; a fifth weighting circuit connected to said second line memory unit for receiving a second delay signal therefrom and for weighting said second delay signal; a sixth weighting circuit connected to said third line memory unit for receiving a third delay signal and for weighting said third delay signal; and a second adder circuit connected to said fourth, fifth, and sixth weighting circuits for receiving the first, second, and third delay signals therefrom and for adding the weighted first, second, and third delay signals, said second comb filter forming a comb filter together with said second and third line memory units of said delay means for generating a second chrominance signal; (d) a third comb filter including: a seventh weighting circuit connected to said third line memory unit for receiving a third delay signal therefrom and for weighting said third delay signal; an eighth weighting circuit connected to said fourth line memory unit for receiving a fourth delay signal therefrom and for weighting said fourth delay signal; and a third adder circuit connected to the seventh and eighth weighting circuits and the third weighting circuit of said first comb filter for adding the weighted second, third, and fourth delay signals, said third comb filter forming a comb filter together with said third and fourth line memory units of said delay means for generating a third chrominance signal; (e) a group of subtraction circuits including first, second, and third subtraction circuits in which: said first subtraction circuit is connected to said input terminal and said second line memory unit for receiving the composite video signal from said input terminal and for receiving said second delay signal from said second line memory unit, thereby generating a first difference signal between said composite video signal and said second delay signal; said second delay circuit is connected to said first line memory unit and said third line memory unit for receiving a first delay signal from said first line memory unit and for receiving a third delay signal from said third line memory unit, thereby generating a second difference signal between said first delay signal and said third delay signal; and said third subtraction circuit is connected to said second and fourth line memory units for receiving a second delay signal from said second line memory unit and for receiving a fourth delay signal from said fourth line memory unit, thereby generating a third difference signal between said second delay signal and said fourth delay signal; (f) a minimum value detecting circuit connected to the first, second, and third subtraction circuits of said subtraction circuit group for receiving the first, second, and third difference signals from said first, second, and third subtraction circuits, respectively, said minimum value detecting circuit generating a first output signal when the value of the first difference signal is less than the values of the third and second difference signals, generating a second output signal when the value of the second difference signal is less than the values of the first and third difference signals, and generating a third output signal when the value of the third difference signal is less than the values of the first and second difference signals; (g) switch means connected to said first, second, and third comb filters for receiving the first, second and third chrominance signals therefrom, said switch means being further connected to said minimum value detecting circuit for receiving said first, second, and third output signals therefrom, said switch means selecting and outputting the first chrominance signal when the first output signal is supplied from said minimum value detecting circuit, selecting and outputting the second chrominance signal when the second output signal is supplied, and selecting and outputting the third chrominance signal when the third output signal is supplied; and (h) a band-pass filter connected to said switch means for receiving therefrom the first, second, or third chrominance signal selected by said switch means and for filtering said chrominance signal, thereby supplying the filtered chrominance signal to an output terminal.

Claim 3

A circuit according to claim 1 wherein the composite signal supplied to the input terminal connected to said signal delay means is a digitized signal.

Claim 4

A circuit according to claim 1 wherein: the weight of the first, third, fourth, sixth, and eighth weighting circuits is -1/4; the weight of the second, fifth, and seventh weighting circuits is 1/2; a first inverter is connected between said first comb filter and said first adder circuit; and a second inverter is connected between said third comb filter and said third adder circuit.

Claim 5

A circuit having comb filters for separating a luminance signal or a chrominance signal from a composite signal of TV signals in the NTSC system comprising: (a) signal delay means including first, second, third, and fourth line memory units each being sequentially connected in series, a delay time of each said line memory unit being identical to a horizontal scanning pariod, and said first line memory unit being connected to an input terminal to which the composite signal is supplied; (b) a first comb filter including; a first weighting circuit c nnected to said input terminal for receiving the composite video signal from said input terminal and for weighting the composite video signal; a second weighting circuit connected to said first line memory unit for receiving a first delay signal therefrom and for weighting said first delay signal; a third weighting circuit connected to said second line memory unit for receiving a second delay signal therefrom and for weighting said second delay signal; and a first adder circuit connected to said first, second, and third weighting circuits for adding said weighted composite signal and said weighted first and second delay signals, said first comb filter forming a comb filter together with said first and second line memory units of said signal delay means for generating a first chrominance signal; (c) a second comb filter comprising: a fourth weighting circuit connected to said first line memory unit for receiving a first delay signal therefrom and for weighting said first delay signal; a fifth weighting circuit connected to said second line memory unit for receiving a second delay signal therefrom and for weighting said second delay signal; a sixth weighting circuit connected to said third line memory unit for receiving a third delay signal and for weighting said third delay signal; and a second adder circuit connected to said fourth, fifth, and sixth weighting circuits for receiving the first, second, and third delay signals therefrom and for adding the weighted first, second, and third delay signals, said second comb filter forming a comb filter together with said second and third line memory units of said delay means for generating a second chrominance signal; (d) a third comb filter including: a seventh weighting circuit connected to said third line memory unit for receiving a third delay signal therefrom and for weighting said third delay signal; an eighth weighting circuit connected to said fourth line memory unit for receiving a fourth delay signal therefrom and for weighting said fourth delay signal; and a third adder circuit connected to the seventh and eighth weighting circuits and the third weighting circuit of said first comb filter for adding the weighted second, third, and fourth delay signals, said third comb filter forming a comb filter together with said third and fourth line memory units of said delay means for generating a third chrominance signal; (e) a group of subtraction circuits including first, second, and third subtraction circuits in which: said first subtraction circuit is connected to said input terminal and said second line memory unit for receiving the composite video signal from said input terminal and for receiving said second delay signal from said second line memory unit, thereby generating a first difference signal between said composite video signal and said second delay signal; said second delay circuit is connected to said first line memory unit and said third line memory unit for receiving a first delay signal from said first line memory unit and for receiving a third delay signal from said third line memory unit, thereby generating a second difference signal between said first delay signal and said third delay signal; and said third subtraction circuit is connected to said second and fourth line memory units for receiving a second delay signal from said second line memory unit and for receiving a fourth delay signal from said fourth line memory unit, thereby generating a third difference signal between said second delay signal and said fourth delay signal; (f) a minimum value detecting circuit connected to the first, second, and third subtraction circuits of said subtraction circuit group for receiving the first, second, and third difference signals from said first, second, and third subtraction circuits, respectively, said minimum value detecting circuit generating a first output signal when the value of the first difference signal is less than the values of the third and second difference signals, generating a second output signal when the value of the second difference signal is less than the values of the first and third difference signals, and generating a third output signal when the value of the third difference signal is less than the values of the first and second difference signals; (g) switch means connected to said first, second, and third comb filters for receiving the first, second and third chrominance signals therefrom, said switch means being further connected to said minimum value detecting circuit for receiving said first, second, and third output signals therefrom, said switch means selecting and outputting the first chrominance signal when the first output signal is supplied from said minimum value detecting circuit, selecting and outputting the second chrominance signal when the second output signal is supplied, and selecting and outputting the third chrominance signal when the third output signal is supplied; (h) a band-pass filter connected to said switch means for receiving therefrom the first, second, or third chrominance signal selected by said switch means and for filtering said chrominance signal, thereby supplying the filtered chrominance signal to an output terminal; and (i) subtraction means connected to the second line memory unit of said signal delay means and said band-pass filter for subtracting the chrominance signal filtered through said band-pass filter from said second delay signal, thereby generating a luminance signal.

Claim 6

A circuit having comb filters for separating a luminance signal or a chrominance signal from a composite signal of TV signals in the NTSC system comprising: (a) signal delay means including first, second, third, and fourth line memory units each being sequentially connected in series, a delay time of each said line memory unit being identical to a horizontal scanning pariod, and said first line memory unit being connected to an input terminal to which the composite signal is supplied; (b) a first comb filter including; a first weighting circuit c nnected to said input terminal for receiving the composite video signal from said input terminal and for weighting the composite video signal; a second weighting circuit connected to said first line memory unit for receiving a first delay signal therefrom and for weighting said first delay signal; a third weighting circuit connected to said second line memory unit for receiving a second delay signal therefrom and for weighting said second delay signal; and a first adder circuit connected to said first, second, and third weighting circuits for adding said weighted composite signal and said weighted first and second delay signals, said first comb filter forming a comb filter together with said first and second line memory units of said signal delay means for generating a first chrominance signal; (c) a second comb filter comprising: a fourth weighting circuit connected to said first line memory unit for receiving a first delay signal therefrom and for weighting said first delay signal; a fifth weighting circuit connected to said second line memory unit for receiving a second delay signal therefrom and for weighting said second delay signal; a sixth weighting circuit connected to said third line memory unit for receiving a third delay signal and for weighting said third delay signal; and a second adder circuit connected to said fourth, fifth, and sixth weighting circuits for receiving the first, second, and third delay signals therefrom and for adding the weighted first, second, and third delay signals, said second comb filter forming a comb filter together with said second and third line memory units of said delay means for generating a second chrominance signal; (d) a third comb filter including: a seventh weighting circuit connected to said third line memory unit for receiving a third delay signal therefrom and for weighting said third delay signal; an eighth weighting circuit connected to said fourth line memory unit for receiving a fourth delay signal therefrom and for weighting said fourth delay signal; and a third adder circuit connected to the seventh and eighth weighting circuits and the third weighting circuit of said first comb filter for adding the weighted second, third, and fourth delay signals, said third comb filter forming a comb filter together with said third and fourth line memory units of said delay means for generating a third chrominance signal; (e) a group of subtraction circuits including first, second, and third subtraction circuits in which: said first subtraction circuit is connected to said input terminal and said second line memory unit for receiving the composite video signal from said input terminal and for receiving said second delay signal from said second line memory unit, thereby generating a first difference signal between said composite video signal and said second delay signal; said second delay circuit is connected to said first line memory unit and said third line memory unit for receiving a first delay signal from said first line memory unit and for receiving a third delay signal from said third line memory unit, thereby generating a second difference signal between said first delay signal and said third delay signal; and said third subtraction circuit is connected to said second and fourth line memory units for receiving a second delay signal from said second line memory unit and for receiving a fourth delay signal from said fourth line memory unit, thereby generating a third difference signal between said second delay signal and said fourth delay signal; (f) a minimum value detecting circuit connected to the first, second, and third subtraction circuits of said subtraction circuit group for receiving the first, second, and third difference signals from said first, second, and third subtraction circuits, respectively, said minimum value detecting circuit generating a first output signal when the value of the first difference signal is less than the values of the third and second difference signals, generating a second output signal when the value of the second difference signal is less than the values of the first and third difference signals, and generating a third output signal when the value of the third difference signal is less than the values of the first and second difference signals; (g) switch means connected to said first, second, and third comb filters for receiving the first, second and third chrominance signals therefrom, said switch means being further connected to said minimum value detecting circuit for receiving said first, second, and third output signals therefrom, said switch means selecting and outputting the first chrominance signal when the first output signal is supplied from said minimum value detecting circuit, selecting and outputting the second chrominance signal when the second output signal is supplied, and selecting and outputting the third chrominance signal when the third output signal is supplied; (h) a band-pass filter connected to said switch means for receiving therefrom the first, second, or third chrominance signal selected by said switch means and for filtering said chrominance signal, thereby supplying the filtered chrominance signal to an output terminal; and (i) subtraction means connected to the second line memory unit of said signal delay means and said band-pass filter for subtracting the chrominance signal filtered through said band-pass filter from said second delay signal, thereby generating a luminance signal.

Claim 7

A circuit according to claim 4 wherein the composite signal supplied to the input terminal connected to said signal delay means is a digitized signal.

Claim 8

A circuit according to claim 4 wherein: the weight of the first, third, fourth, sixth, and eighth weighting circuits is -1/4; the weight of the second, fifth, and seventh weighting circuits is 1/2; a first inverter is connected between said first comb filter and said first adder circuit; and a second inverter is connected between said third comb filter and said third adder circuit.

Claim 9

A circuit having comb filters for separating a luminance signal or a chromihahce signal from a composite signal of TV signals in the NTSC system comprising: (a) signal delay means including first, second, third, and fourth line memory units each being sequentially connected in series, a delay time of each said line memory unit being identical to a horizontal scanning period, and said first line memory unit being connected to an input terminal to which the composite signal is supplied; (b) a first comb filter including: a first weighting circuit connected to said input terminal for receiving the composite video signal from said input terminal and for weighting the composite video signal; a second weighting circuit connected to said first line memory unit for receiving a first delay signal therefrom and for weighting said first delay signal; a third weighting circuit connected to said second line memory unit for receiving a second delay signal therefrom and for weighting said second delay signal; and a first adder circuit connected to said first, second, and third weighting circuits for adding said weighted composite signal and said weighted first and second delay signals, said first comb filter forming a comb filter together with said first and second line memory units of said signal delay means for generating a first chrominance signal; (c) a second comb filter comprising: a fourth weighting circuit connected to said first line memory unit for receiving a first delay signal therefrom and for weighting said first delay signal; a fifth weighting circuit connected to said second line memory unit for receiving a second delay signal therefrom and for weighting said second delay signal; a sixth weighting circuit connected to said third line memory unit for receiving a third delay signal and for weighting said third delay signal; and a second adder circuit connected to said fourth, fifth, and sixth weighting circuits for receiving the first, second, and third delay signals therefrom and for adding the weighted first, second, and third delay signals, said second comb filter forming a comb filter together with said second and third line memory units of signal; (d) a third comb filter including: a seventh weighting circuit connected to said third line memory unit for receiving a third delay signal therefrom and for weighting said third delay signal; an eighth weighting circuit connected to said fourth line memory unit for receiving a fourth delay signal therefrom and for weighting said fourth delay signal; and a third adder circuit connected to the seventh and eighth weighting circuits and the third weighting circuit of said first comb filter for adding the weighted second, third, and fourth delay signals, said third comb filter forming a comb filter together with said third and fourth line memory units of said delay means for generating a third chrominance signal; (e) a group of subtraction circuits including first, second, and third subtraction circuits in which: said first subtraction circuit is connected to said input terminal and said second line memory unit for receiving the composite video signal from said input terminal and for receiving said second delay signal from said second line memory unit, thereby generating a first difference signal between said composite video signal and said second delay signal; said second delay circuit is connected to said first line memory unit and said third line memory unit for receiving a first delay signal from said first line memory unit and for receiving a third delay signal from said third line memory unit, thereby generating a second difference signal between said first delay signal and said third delay signal; and said third subtraction circuit is connected to said second and fourth line memory units for receiving a second delay signal from said second line memory unit and for receiving a fourth delay signal from said fourth line memory unit, thereby generating a third difference signal between said second delay signal and said fourth delay signal; (f) a minimum value detecting circuit connected to the first, second, and third subtraction circuits of said subtraction circuit group for receiving the first, second, and third difference signals from said first, second, and third subtraction circuits, respectively, said minimum value detecting circuit generating a first output signal when the value of the first difference signal is less than the values of the third and second difference signals, generating a second output signal when the value of the second difference signal is less than the values of the first and third difference signals, and generating a third output signal when the value of the third difference signal is less than the values of the first and second difference signals; (g) first switch means connected to said first, second, and third comb filters for receiving the first, second and third chrominance signals therefrom, said first switch means being further connected to said minimum value detecting circuit for receiving said first, second, and third output signals therefrom, said first switch means selecting and outputting the first chrominance signal when the first output signal is supplied from said minimum value detecting circuit, selecting and outputting the second chrominance signal when the second output signal is supplied, and selecting and outputting the third chrominance signal when the third output signal is supplied; (h) a band-pass filter connected to said first switch means for receiving therefrom the first, second, or third chrominance signal selected by said first switch means and for filtering said chrominance signal, thereby suppling the filtered chrominance signal to an output terminal; (i) a fourth comb filter including: a ninth weighting circuit connected to said input terminal for receiving the composite video signal therefrom and for weighting the composite video signal; a tenth weighting circuit connected to said second line memory unit for receiving a second delay signal therefrom and for weighting the second delay signal; and a fourth adder circuit connected to said ninth and tenth weighting circuits and the second weighting circuit of said first comb filter for adding the output signals from said second, ninth, and tenth weighting circuits, said fourth comb filter forming a comb filter together with the first and second line memory units of said signal delay means for generating a first luminance signal; (j) a fifth comb filter including: a 11th weighting circuit connected to said first line memory unit for receiving a first delay signal therefrom and for weighting the first delay signal; a 12th weighting circuit connected to said third line memory unit for receiving a third delay signal therefrom and for weighting the third delay signal; and a fifth adder circuit connected to said 11th and 12th weighting circuits and the fifth weighting circuit of said second comb filter for adding the output signals from said fifth, 11th, and 12th weighting circuits, said fifth comb filter forming a comb filter together with the second and third line memory units of said signal delay means for generating a second luminance signal; (k) a sixth comb filter including: a 13th weighting circuit connected to said fourth line memory unit for receiving a fourth delay signal therefrom and for weighting the fourth delay signal and a sixth adder circuit connected to said 13th weighting circuit, the tenth weighting circuit of said fouth comb filter, and the seventh weighting circuit of said third comb filter for adding the output signals from said seventh, 10th, and 14th weighting circuits, said sixth comb filter forming a comb filter together with the third and third line memory units of said signal delay means for generating a third luminance signal; and (1) second switch means connected to said fourth, fifth, and sixth comb filters for receiving the first, second and third chrominance signals therefrom, said first switch means being further connected to said minimum value detecting circuit for receiving said first, second, and third output signals therefrom, said second switch means selecting and outputting the first chrominance signal when the first output signal is supplied from said minimum value detecting circuit, selecting and outputting the second chrominance signal when the second output signal is supplied, and selecting and outputting the third chrominance signal when the third output signal is supplied.

Claim 10

A circuit having comb filters for separating a luminance signal or a chromihahce signal from a composite signal of TV signals in the NTSC system comprising: (a) signal delay means including first, second, third, and fourth line memory units each being sequentially connected in series, a delay time of each said line memory unit being identical to a horizontal scanning period, and said first line memory unit being connected to an input terminal to which the composite signal is supplied; (b) a first comb filter including: a first weighting circuit connected to said input terminal for receiving the composite video signal from said input terminal and for weighting the composite video signal; a second weighting circuit connected to said first line memory unit for receiving a first delay signal therefrom and for weighting said first delay signal; a third weighting circuit connected to said second line memory unit for receiving a second delay signal therefrom and for weighting said second delay signal; and a first adder circuit connected to said first, second, and third weighting circuits for adding said weighted composite signal and said weighted first and second delay signals, said first comb filter forming a comb filter together with said first and second line memory units of said signal delay means for generating a first chrominance signal; (c) a second comb filter comprising: a fourth weighting circuit connected to said first line memory unit for receiving a first delay signal therefrom and for weighting said first delay signal; a fifth weighting circuit connected to said second line memory unit for receiving a second delay signal therefrom and for weighting said second delay signal; a sixth weighting circuit connected to said third line memory unit for receiving a third delay signal and for weighting said third delay signal; and a second adder circuit connected to said fourth, fifth, and sixth weighting circuits for receiving the first, second, and third delay signals therefrom and for adding the weighted first, second, and third delay signals, said second comb filter forming a comb filter together with said second and third line memory units of signal; (d) a third comb filter including: a seventh weighting circuit connected to said third line memory unit for receiving a third delay signal therefrom and for weighting said third delay signal; an eighth weighting circuit connected to said fourth line memory unit for receiving a fourth delay signal therefrom and for weighting said fourth delay signal; and a third adder circuit connected to the seventh and eighth weighting circuits and the third weighting circuit of said first comb filter for adding the weighted second, third, and fourth delay signals, said third comb filter forming a comb filter together with said third and fourth line memory units of said delay means for generating a third chrominance signal; (e) a group of subtraction circuits including first, second, and third subtraction circuits in which: said first subtraction circuit is connected to said input terminal and said second line memory unit for receiving the composite video signal from said input terminal and for receiving said second delay signal from said second line memory unit, thereby generating a first difference signal between said composite video signal and said second delay signal; said second delay circuit is connected to said first line memory unit and said third line memory unit for receiving a first delay signal from said first line memory unit and for receiving a third delay signal from said third line memory unit, thereby generating a second difference signal between said first delay signal and said third delay signal; and said third subtraction circuit is connected to said second and fourth line memory units for receiving a second delay signal from said second line memory unit and for receiving a fourth delay signal from said fourth line memory unit, thereby generating a third difference signal between said second delay signal and said fourth delay signal; (f) a minimum value detecting circuit connected to the first, second, and third subtraction circuits of said subtraction circuit group for receiving the first, second, and third difference signals from said first, second, and third subtraction circuits, respectively, said minimum value detecting circuit generating a first output signal when the value of the first difference signal is less than the values of the third and second difference signals, generating a second output signal when the value of the second difference signal is less than the values of the first and third difference signals, and generating a third output signal when the value of the third difference signal is less than the values of the first and second difference signals; (g) first switch means connected to said first, second, and third comb filters for receiving the first, second and third chrominance signals therefrom, said first switch means being further connected to said minimum value detecting circuit for receiving said first, second, and third output signals therefrom, said first switch means selecting and outputting the first chrominance signal when the first output signal is supplied from said minimum value detecting circuit, selecting and outputting the second chrominance signal when the second output signal is supplied, and selecting and outputting the third chrominance signal when the third output signal is supplied; (h) a band-pass filter connected to said first switch means for receiving therefrom the first, second, or third chrominance signal selected by said first switch means and for filtering said chrominance signal, thereby suppling the filtered chrominance signal to an output terminal; (i) a fourth comb filter including: a ninth weighting circuit connected to said input terminal for receiving the composite video signal therefrom and for weighting the composite video signal; a tenth weighting circuit connected to said second line memory unit for receiving a second delay signal therefrom and for weighting the second delay signal; and a fourth adder circuit connected to said ninth and tenth weighting circuits and the second weighting circuit of said first comb filter for adding the output signals from said second, ninth, and tenth weighting circuits, said fourth comb filter forming a comb filter together with the first and second line memory units of said signal delay means for generating a first luminance signal; (j) a fifth comb filter including: a 11th weighting circuit connected to said first line memory unit for receiving a first delay signal therefrom and for weighting the first delay signal; a 12th weighting circuit connected to said third line memory unit for receiving a third delay signal therefrom and for weighting the third delay signal; and a fifth adder circuit connected to said 11th and 12th weighting circuits and the fifth weighting circuit of said second comb filter for adding the output signals from said fifth, 11th, and 12th weighting circuits, said fifth comb filter forming a comb filter together with the second and third line memory units of said signal delay means for generating a second luminance signal; (k) a sixth comb filter including: a 13th weighting circuit connected to said fourth line memory unit for receiving a fourth delay signal therefrom and for weighting the fourth delay signal and a sixth adder circuit connected to said 13th weighting circuit, the tenth weighting circuit of said fouth comb filter, and the seventh weighting circuit of said third comb filter for adding the output signals from said seventh, 10th, and 14th weighting circuits, said sixth comb filter forming a comb filter together with the third and third line memory units of said signal delay means for generating a third luminance signal; and (1) second switch means connected to said fourth, fifth, and sixth comb filters for receiving the first, second and third chrominance signals therefrom, said first switch means being further connected to said minimum value detecting circuit for receiving said first, second, and third output signals therefrom, said second switch means selecting and outputting the first chrominance signal when the first output signal is supplied from said minimum value detecting circuit, selecting and outputting the second chrominance signal when the second output signal is supplied, and selecting and outputting the third chrominance signal when the third output signal is supplied.

Claim 11

A circuit according to claim 7 wherein the composite signal supplied to the input terminal connected to said signal delay means is a digitized signal.

Claim 12

A circuit according to claim 7 wherein: the weight of the first, third, fourth, sixth, and eighth weighting circuits is -1/4;

Claim 13

the weight of the second, fifth, and seventh weighting circuits is 1/2;

Claim 14

the weight of the second, fifth, and seventh weighting circuits is 1/2;

Claim 15

the weight of said ninth, tenth, 11th, 12th, and 13th weighting circuit is 1/4; a first inverter is connected between said first comb filter and said first adder circuit; and a second inverter is connected between said third comb filter and said third adder circuit.

Claim 16

the weight of said ninth, tenth, 11th, 12th, and 13th weighting circuit is 1/4; a first inverter is connected between said first comb filter and said first adder circuit; and a second inverter is connected between said third comb filter and said third adder circuit.