US4707654A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit having input and output terminals for testing
Assignee: Hitachi Ltd
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Filing: 1985-09-06
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Granted: 1987-11-17
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Expires: 2005-09-06
Abstract
Abstract An integrated circuit is constructed in order that tests can be conducted on a plurality of circuits to determine which of the circuits is defective. In particular, the circuit is constructed to allow such testing with the use of fewer input and output pins for testing. To accomplish this, a first buffer gate circuit, a resistor, and a second buffer gate are connected in series in the order mentioned between the output terminal of a first circuit and the input terminal of a second circuit. An input and output terminal pin for testing is located at a junction point of the resistor and second buffer gate.
Inventors
- 👤 Toshiro Suzuki
- 👤 Fumiaki Fujii
- 👤 Izuru Yamada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 16:52
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31701
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
111 words
An integrated circuit comprising: at least a first circuit and a second circuit to be connected in series; a first buffer gate, a resistor, and a second buffer gate connected between an output terminal of said first circuit and an input terminal of said second circuit in the order mentioned; and means for allowing testing of the output of the first circuit and for allowing the application of an input test signal to said second circuit without said input test signal having to pass through said first circuit, said means comprising an input/output terminal pin for test signals provided at a junction point of said resistor and said second buffer gate.
Claim 2
Dependent Claim
111 words
An integrated circuit comprising: at least a first circuit and a second circuit to be connected in series; a first buffer gate, a resistor, and a second buffer gate connected between an output terminal of said first circuit and an input terminal of said second circuit in the order mentioned; and means for allowing testing of the output of the first circuit and for allowing the application of an input test signal to said second circuit without said input test signal having to pass through said first circuit, said means comprising an input/output terminal pin for test signals provided at a junction point of said resistor and said second buffer gate.
Claim 3
Dependent Claim
25 words
An integrated circuit according to claim 1, wherein said first circuit is an analog/digital converting circuit and said second circuit is a digital/digital converting circuit.
Claim 4
Dependent Claim
47 words
An integrated circuit according to claim 1, wherein said second buffer gate is comprised of MOS transistors, and wherein an input protection circuit is connected between said resistor and an input terminal of said second buffer gate to protect said MOS transistors of said second buffer gate.
Claim 5
Dependent Claim
16 words
An integrated circuit according to claim 1, wherein said integrated circuit is formed in a chip.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-11-16 | 1991-05-18 | 1991-11-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-11-16 | 1995-05-18 | 1995-11-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-11-16 | 1999-05-18 | 1999-11-17 | $7700.00 | Window Closed / Lapsed |