Patent US4705035A successfully refreshed from Google Patents.
US4705035A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Parallax-free optical zone marker
Assignee: Becton Dickinson and Co
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Filing: 1986-09-02
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Granted: 1987-11-10
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Expires: 2006-09-02
Abstract
Abstract A parallax-free optical zone marker for use in radial karatotomy cornea surgery for impressing a temporary circular indentation into the cornea, the circular indentation to be used as a reference for radial incisions therefrom. The marker, integrally molded, includes an elongated handle and a collar portion disposed at one end of the handle. The lower end margin of the collar is preferrably circular an adapted to impress the circular indentation into the cornea with normal hand pressure applied through the handle. A passageway extends through the collar from its upper end margin to its lower end margin. Disposed within the passageway are a pair of crossplanes intersecting, preferably at ninety degrees one to another, along the longitudinal axis of the passageway, which axis intersects the center of the circular lower end margin. These crossplanes extend along substantially the entire length of the passageway but not to the lower end margin of the collar so as to prevent contact of the crossplanes with the cornea. The intersection of the crossplanes provides the user with viewable alignment means for assisting in the accurate orientation of the circular indentation. These crossplanes preferably taper in thickness toward their intersection for enhanced accuracy in the placement of the circular indentation. The marker is molded preferably of plastic in a wide range of sizes and may also be molded of clear or translucent material to increase light availability to the cornea as the circular indentation is made.
Inventors
- 👤 Thomas B. Givens
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 07:38
CPC Classifications
A; A61; A61F; A61F9/00; A61F9/007; A61F9/013; A61F9/0136; A61B; A61B90/00; A61B90/39; A61B2090/3937
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
342 words
A BICMOS logic circuit comprising: a first input terminal; a second input terminal; an output terminal; a first voltage terminal; a second voltage terminal; a first bipolar transistor having its collector-emitter path coupled between said first voltage terminal and said output terminal and having a base; a second bipolar transistor having its collector-emitter path coupled between said output terminal and said second voltage terminal and having a base; a first CMOS transistor having its source-drain current path coupled between said first voltage terminal and said base of said first bipolar transistor and a gate; a second CMOS transistor having its source-drain current path coupled between said said base of said first bipolar transistor and said second voltage terminal and a gate; a third CMOS transistor having a gate, a source and a drain; a fourth CMOS transistor having its source-drain current path coupled between said base of said second bipolar transistor and said second voltage terminal and a gate coupled to said base of said first bipolar transistor; first transmission means coupled between said first input terminal and said gates of said first, second, and third CMOS transistors and coupled to said second input terminal for coupling said first input terminal to said gates of said first, second and third CMOS transistors in response to an input signal on said second input terminal; a fifth CMOS transistor having its source-drain current path coupled between said first voltage terminal and said gate of said first CMOS transistor and a gate coupled to said second input terminal; a sixth CMOS transistor having its source-drain current path coupled to said source-drain current path of said third CMOS transistor, said source-drain current paths of said third and sixth CMOS transistors coupled between said output terminal and said base of said second bipolar transistor, and a gate coupled to said second input terminal; and a seventh CMOS transistor having its source-drain current path coupled between said base of said second bipolar transistor and said second voltage terminal and a gate coupled to said said second input terminal.
Claim 2
Dependent Claim
342 words
A BICMOS logic circuit comprising: a first input terminal; a second input terminal; an output terminal; a first voltage terminal; a second voltage terminal; a first bipolar transistor having its collector-emitter path coupled between said first voltage terminal and said output terminal and having a base; a second bipolar transistor having its collector-emitter path coupled between said output terminal and said second voltage terminal and having a base; a first CMOS transistor having its source-drain current path coupled between said first voltage terminal and said base of said first bipolar transistor and a gate; a second CMOS transistor having its source-drain current path coupled between said said base of said first bipolar transistor and said second voltage terminal and a gate; a third CMOS transistor having a gate, a source and a drain; a fourth CMOS transistor having its source-drain current path coupled between said base of said second bipolar transistor and said second voltage terminal and a gate coupled to said base of said first bipolar transistor; first transmission means coupled between said first input terminal and said gates of said first, second, and third CMOS transistors and coupled to said second input terminal for coupling said first input terminal to said gates of said first, second and third CMOS transistors in response to an input signal on said second input terminal; a fifth CMOS transistor having its source-drain current path coupled between said first voltage terminal and said gate of said first CMOS transistor and a gate coupled to said second input terminal; a sixth CMOS transistor having its source-drain current path coupled to said source-drain current path of said third CMOS transistor, said source-drain current paths of said third and sixth CMOS transistors coupled between said output terminal and said base of said second bipolar transistor, and a gate coupled to said second input terminal; and a seventh CMOS transistor having its source-drain current path coupled between said base of said second bipolar transistor and said second voltage terminal and a gate coupled to said said second input terminal.
Claim 3
Dependent Claim
26 words
The BICMOS logic circuit according to claim 1 further comprising an inverter coupled between said second input terminal and said gate of said fifth CMOS transistor.
Claim 4
Dependent Claim
42 words
The BICMOS logic circuit according to claim 1 further comprising second transmisison means coupled between said base of said first bipolar transistor and said output terminal and coupled to said second input terminal for increasing the voltage swing on said output terminal.
Claim 5
Dependent Claim
343 words
A BICMOS logic circuit comprising: a first input terminal; a second input terminal; an output terminal; a first voltage terminal; a second voltage terminal; a first bipolar transistor having its collector-emitter path coupled between said first voltage terminal and said output terminal and having a base; a second bipolar transistor having its collector-emitter path coupled between said output terminal and said second voltage terminal and having a base; a first CMOS transistor having a gate coupled to said first input terminal and a source-drain current path; a second CMOS transistor having its source-drain current path coupled between said base of said first bipolar transistor and said second voltage terminal and a gate coupled to said first input terminal; a third CMOS transistor having a gate coupled to said input terminal and a source-drain current path; and a fourth CMOS transistor having its source-drain current path coupled between said base of said second bipolar transistor and said second voltage terminal and a gate coupled to said first input terminal; a fifth CMOS transistor having a gate coupled to said second input terminal and its source-drain current path coupled to said source-drain current path of said first CMOS transistor, said source-drain current path of said third and sixth CMOS transistors coupled between said first voltage terminal and said base of said first bipolar transistor; a sixth CMOS transistor having its source-drain current path coupled between said base of said first bipolar transistor and said second voltage terminal and a gate coupled to said second input terminal; a seventh CMOS transistor having a gate coupled to said second input terminal and its source-drain current path coupled to said source-drain current path of said third CMOS transistor, said source-drain current paths of said third and seventh CMOS transistors coupled between said output terminal and said base of said second bipolar transistor; and an eighth CMOS transistor having its source-drain current path coupled between said base of said second bipolar transistor and said second voltage terminal and a gate coupled to said base of said first bipolar transistor.
Claim 6
Dependent Claim
343 words
A BICMOS logic circuit comprising: a first input terminal; a second input terminal; an output terminal; a first voltage terminal; a second voltage terminal; a first bipolar transistor having its collector-emitter path coupled between said first voltage terminal and said output terminal and having a base; a second bipolar transistor having its collector-emitter path coupled between said output terminal and said second voltage terminal and having a base; a first CMOS transistor having a gate coupled to said first input terminal and a source-drain current path; a second CMOS transistor having its source-drain current path coupled between said base of said first bipolar transistor and said second voltage terminal and a gate coupled to said first input terminal; a third CMOS transistor having a gate coupled to said input terminal and a source-drain current path; and a fourth CMOS transistor having its source-drain current path coupled between said base of said second bipolar transistor and said second voltage terminal and a gate coupled to said first input terminal; a fifth CMOS transistor having a gate coupled to said second input terminal and its source-drain current path coupled to said source-drain current path of said first CMOS transistor, said source-drain current path of said third and sixth CMOS transistors coupled between said first voltage terminal and said base of said first bipolar transistor; a sixth CMOS transistor having its source-drain current path coupled between said base of said first bipolar transistor and said second voltage terminal and a gate coupled to said second input terminal; a seventh CMOS transistor having a gate coupled to said second input terminal and its source-drain current path coupled to said source-drain current path of said third CMOS transistor, said source-drain current paths of said third and seventh CMOS transistors coupled between said output terminal and said base of said second bipolar transistor; and an eighth CMOS transistor having its source-drain current path coupled between said base of said second bipolar transistor and said second voltage terminal and a gate coupled to said base of said first bipolar transistor.
Claim 7
Dependent Claim
26 words
The BICMOS logic circuit according to claim 4 further comprising an inverter coupled between said first input terminal and said gate of said third CMOS transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-11-09 | 1991-05-11 | 1991-11-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-11-09 | 1995-05-11 | 1995-11-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-11-09 | 1999-05-11 | 1999-11-10 | $7700.00 | Window Closed / Lapsed |