Patent US4703553A successfully refreshed from Google Patents.
← Back to Patent Explorer
US4703553A Expired / Lapsed US ⏱️ 0.0 years remaining

Drive through doping process for manufacturing low back surface recombination solar cells

Assignee: The AT&T MVPD Group LLC
•
Filing: 1986-06-16
•
Granted: 1987-11-03
•
Expires: 2006-06-16
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A method for providing deep impurity doped regions under the back contacts of a solar cell. In a semiconductor wafer with a p-n junction therein defining an n+ layer emitter and p-type layer bulk, a p+ layer is formed in the p-type layer under the back surface of the wafer. An oxide passivation layer is disposed over the back surface. Metal paste is screen printed onto the oxide layer in a predetermined pattern. The combination is heated to a temperature such that the metal paste will drive through the oxide layer and alloy with selected regions of p+ layer and p-type layer to a predetermined depth forming heavily doped p+ impurity regions. Metallization is applied onto the oxide layer making electrical contact with the heavily doped p+ impurity regions.

Inventors

  • 👤 Nick Mardesich

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 12:16
CPC Classifications
H; H10; H10F; H10F10/00; H10F10/10; H10F10/14; H10F71/00; H10F71/121; H10F77/00; H10F77/20; H10F77/206; H10F77/211; H10F77/30; H10F77/306; H10F77/311; Y; Y02; Y02E; Y02E10/00; Y02E10/50; Y02E10/547; Y02P; Y02P70/00; Y02P70/50

Claims Analysis

Total Claims: 21
Claim 1
Independent Claim 256 words
A method for passivating the back metallization of a solar cell and forming deep impurity doped regions under the back contacts of said solar cell, said method comprising the steps of: providing a p-type wafer of semiconductor material with a front and a back essentially parallel major surfaces; forming an n+ layer under the front major surface of said wafer defining an n + -p junction between the front and back major surfaces; forming a p+ layer under the back surface of said wafer defining a p + -p junction between the front and back major parallel surfaces, the p + -p junction and the n + -p junction defining a p-type layer therebetween; depositing a nonconductive layer on said major surface, said nonconductive layer having an exposed major surface essentially parallel to said back major surface; depositing a metal paste in a predetermined pattern onto the exposed major surface of said nonconductive layer; heating said wafer and said metal paste to a predetermined temperature so that said metal paste will oxidize, thus reducing the portion of said nonconductive layer located underneath said metal paste pattern, which remaining metal will continue melting into and alloying with portions of said p+ layer and portions of the p-type layer to a predetermined depth which is dependent on the temperature, time of heating and amount of metal paste used; and cooling said wafer to form p+ type impurity doped regions in a predetermined pattern extending from the back surface of said wafer into said wafer to a predetermined depth.
Claim 2
Independent Claim 256 words
A method for passivating the back metallization of a solar cell and forming deep impurity doped regions under the back contacts of said solar cell, said method comprising the steps of: providing a p-type wafer of semiconductor material with a front and a back essentially parallel major surfaces; forming an n+ layer under the front major surface of said wafer defining an n + -p junction between the front and back major surfaces; forming a p+ layer under the back surface of said wafer defining a p + -p junction between the front and back major parallel surfaces, the p + -p junction and the n + -p junction defining a p-type layer therebetween; depositing a nonconductive layer on said major surface, said nonconductive layer having an exposed major surface essentially parallel to said back major surface; depositing a metal paste in a predetermined pattern onto the exposed major surface of said nonconductive layer; heating said wafer and said metal paste to a predetermined temperature so that said metal paste will oxidize, thus reducing the portion of said nonconductive layer located underneath said metal paste pattern, which remaining metal will continue melting into and alloying with portions of said p+ layer and portions of the p-type layer to a predetermined depth which is dependent on the temperature, time of heating and amount of metal paste used; and cooling said wafer to form p+ type impurity doped regions in a predetermined pattern extending from the back surface of said wafer into said wafer to a predetermined depth.
Claim 3
Dependent Claim 25 words
The method as recited in claim 1 wherein said metal paste is composed of fine metal particles about 2.0 to about 10 micrometers in diameter.
Claim 4
Dependent Claim 26 words
The method as recited in claim 1 wherein said wafer and metal paste are heated to a temperature between about 680° C. and about 1000° C.
Claim 5
Dependent Claim 28 words
The method as recited in claim 1 wherein said p+ layer formed under the back surface of said wafer is about 0.05 to about 0.3 microns in thickness.
Claim 6
Dependent Claim 35 words
The method as recited in claim 1 wherein said p+ impurity doped regions extend from the back major surface of said wafer to a depth of about 3 to about 15 micrometers into said wafer.
Claim 7
Dependent Claim 14 words
The method as recited in claim 1 wherein said nonconductive layer is an oxide.
Claim 8
Dependent Claim 14 words
The method as recited in claim 6 wherein said nonconductive layer is silicon oxide.
Claim 9
Dependent Claim 14 words
The method as recited in claim 1 wherein said nonconductive layer is silicon nitride.
Claim 10
Dependent Claim 35 words
The method as recited in claim 1 wherein said depositing of said metal paste is accomplished by screen printing said metal paste on the exposed major surface of said nonconductive layer in a predetermined pattern.
Claim 11
Independent Claim 345 words
A method for passivating the back metallization of a solar cell and forming deep impurity doped regions under the back contacts of said solar cell, said method comprising the steps of: providing a p-type wafer of silicon with front and back major essentially parallel surfaces; forming an n + -p junction in said wafer under the front major surface, said junction being disposed between the front and back major surfaces and defining an n+ layer between said junction and the front major surface; maintaining said wafer at a predetermined temperature in the presence of a p-type impurity for a predetermined period of time to produce a p+ layer under said back surface, said p+ layer and said n+ layer defining a p-type layer therebetween; depositing a nonconductive layer upon said back major surface, said nonconductive layer having an exposed major surface essentially parallel to said back major surface; screen printing a metal paste in a predetermined pattern onto the exposed major surface of said nonconductive layer, said metal paste comprising fine metal particles suspended in a vehicle; heating said wafer and metal paste to a predetermined temperature so that said metal paste will oxidize, thus reducing the portion of said nonconductive layer located underneath said metal paste pattern, which remaining metal will continue melting into and alloying with portions of said p+ layer and with portions of said p-type layer to a predetermined depth which is dependent on the temperature and time, and amount of metal paste used; cooling said wafer to form p+ impurity doped regions that extend from at or near said back major surface of said wafer to a predetermined depth into said p-type layer; removing any excess metal and oxide layers formed during the above steps, leaving said nonconductive layer with openings therein extending from the exposed major surface of said nonconductive layer to said p+ impurity doped regions; and applying an electrically conductive material to the exposed major surface of said nonconductive layer in a predetermined pattern, said electrically conductive material making electrical contact to the p+ impurity doped regions.
Claim 12
Independent Claim 345 words
A method for passivating the back metallization of a solar cell and forming deep impurity doped regions under the back contacts of said solar cell, said method comprising the steps of: providing a p-type wafer of silicon with front and back major essentially parallel surfaces; forming an n + -p junction in said wafer under the front major surface, said junction being disposed between the front and back major surfaces and defining an n+ layer between said junction and the front major surface; maintaining said wafer at a predetermined temperature in the presence of a p-type impurity for a predetermined period of time to produce a p+ layer under said back surface, said p+ layer and said n+ layer defining a p-type layer therebetween; depositing a nonconductive layer upon said back major surface, said nonconductive layer having an exposed major surface essentially parallel to said back major surface; screen printing a metal paste in a predetermined pattern onto the exposed major surface of said nonconductive layer, said metal paste comprising fine metal particles suspended in a vehicle; heating said wafer and metal paste to a predetermined temperature so that said metal paste will oxidize, thus reducing the portion of said nonconductive layer located underneath said metal paste pattern, which remaining metal will continue melting into and alloying with portions of said p+ layer and with portions of said p-type layer to a predetermined depth which is dependent on the temperature and time, and amount of metal paste used; cooling said wafer to form p+ impurity doped regions that extend from at or near said back major surface of said wafer to a predetermined depth into said p-type layer; removing any excess metal and oxide layers formed during the above steps, leaving said nonconductive layer with openings therein extending from the exposed major surface of said nonconductive layer to said p+ impurity doped regions; and applying an electrically conductive material to the exposed major surface of said nonconductive layer in a predetermined pattern, said electrically conductive material making electrical contact to the p+ impurity doped regions.
Claim 13
Dependent Claim 27 words
The method as recited in claim 10 wherein said fine metal particles are aluminum particles on the order of about 2.0 to about 10 micrometers in diameter.
Claim 14
Dependent Claim 26 words
The method as recited in claim 10 wherein said wafer and metal paste are heated to a temperature between about 680° C. to about 1000° C.
Claim 15
Dependent Claim 26 words
The method as recited in claim 10, wherein said p+ layer formed in the back major surface is about 0.05 to about 0.3 microns in thickness.
Claim 16
Dependent Claim 35 words
The method as recited in claim 12 wherein said p+ impurity doped regions extend from the back major surface of the wafer to a depth of about 3 to about 15 micrometers into said wafer.
Claim 17
Dependent Claim 14 words
The method as recited in claim 10 wherein said nonconductive layer is an oxide.
Claim 18
Dependent Claim 14 words
The method as recited in claim 15 wherein said nonconductive layer is silicon oxide.
Claim 19
Dependent Claim 14 words
The method as recited in claim 10 wherein said nonconductive layer is silicon nitride.
Claim 20
Dependent Claim 27 words
The method as recited in claim 10 wherein said metal paste predetermined pattern is dots covering less than 1% of the exposed surface of the nonconductive layer.
Claim 21
Dependent Claim 15 words
The method as recited in claim 10 wherein said metal paste predetermined pattern is lines.

References Cited (Backward Citations)

US3903427A Cited
US3990097A Cited
US4106047A Cited
US4165241A Cited
US4163678A Cited
US4234352A Cited
US4278831A Cited
US4395583A Cited
JPS58157175A Cited
JPS5932179A Cited
US4602120A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1990-11-02 1991-05-04 1991-11-03 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1994-11-02 1995-05-04 1995-11-03 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1998-11-02 1999-05-04 1999-11-03 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag