Multi-direction time division multiplex communication apparatus

Claim 1

A multi-direction time division multiplex communication apparatus for a central station in a multi-direction time division multiplex communication system in which the central station transmits signals meant for each of satellite stations in a time division multiplex broadcast mode, while each of the satellite stations after extraction of a clock extracts the signal meant for the own station and intermittently transmits signals from the own station after adjusting the signals to such a timing that, when the signals from the own station reach the satellite station, the signals do not overlap with signals reaching the central station from the other satellite stations and appear as orderly as a single sequence of time division multiplex signals, said apparatus comprising: a demodulator for demodulating a received signal which is transmitted from any of the satellite stations; a plurality of code regenerator circuits each for producing a digital signal by identifying a ONE and a ZERO of an output of said demodulator which is a digital signal; a plurality of temporary storages associated in one-to-one correspondence with said code regenerator circuits for temporarily storing an output of the associated code regenerator circuit; a clock phase delay unit for producing a plurality of clock signals each of which is delayed in phase to a degree different from the others relative to a clock timing of a central station clock signal, which is applied to said clock phase delay unit, said clock signals having different timings being applied as decision clock signals to the code regenerator circuits in one-to-one correspondence; a clock extractor circuit for extracting a received clock signal from the output of the demodulator; a phase comparator for comparing a phase of an output clock signal of said clock extractor circuit with a phase of the central station clock signal; a sample-hold circuit for sample-holding an output of said phase comparator burst by burst; and a selector circuit for selecting an output of one of the temporary storages which has the smallest error rate responsive to an output of said sample-hold circuit.