Ultra high density pad array chip carrier

Claim 1

An improved chip carrier arrangement for mounting a semiconductor chip and accommodating a protective cover, the chip carrier comprising in combination: single, prefired ceramic substrate means forming a base to which a cover attaches and which has an array of conductive through-holes, each through-hole surrounded by conductors on both top and bottom major surfaces and plugged by solder plugs substantially therethrough other than on the top surface, so as to electrically connect, via a plurality of conductive runners that outwardly extend on the top surface, to an arrangement of pads near the periphery of the top surface thereof; and single, flexible dielectric layer means placed as a solid sheet on and affixed to said single, pre-fired ceramic substrate means within the arrangement of pads, for covering said array of through-holes plugged by solder plugs substantially therethrough other than on the top surface as well as a portion of said plurality of conductive runners, and having a top surface for affixing a semiconductor chip. said single, flexible dielectric layer means providing electrically insulative mounting of a semiconductor chip to allow utilization of the area thereunder for said plurality of conductive runners, and said solder plugged through-holes forming a pad array interface on the bottom surface of said single, pre-fired ceramic substrate means as well as providing a hermetic seal for each through-hole therein, whereby the chip carrier arrangement exhibits significantly greater pad array density.