Musical scale generating circuit

Claim 2

A musical scale generating circuit comprising: a oscillator circuit for providing a clock signal; a programmable frequency divider for dividing said clock signal; a frequency dividing ratio data output circuit for providing frequency dividing ratio data determinative of a plurality of frequency dividing ratios of said programmable frequency divider; a frequency dividing ratio discriminating circuit responsive to an output signal from said frequency dividing ratio data output circuit for detecting whether a frequency dividing ratio for providing desired scale frequency is an odd number and providing an output signal; a frequency dividing ratio correcting circuit responsive to said output signal from said frequency dividing ratio discriminating circuit for correcting said frequency dividing ratio by one of incrementing and decrementing when an odd-number frequency is detected by said frequency dividing ratio discriminating circuit and applying a signal corresponding to said corrected dividing ratio to said programmable frequency divider to set the dividing ratio; a one-half frequency divider for dividing an output signal from said programmable frequency divider by two; and a tone generating circuit for generating a tone in response to an output signal from said programmable frequency divider.

Claim 3

A musical scale generating circuit according to claim 1, wherein said frequency dividing ratio output circuit is so set as to output data indicative of a frequency dividing ratio nearest to one-half a frequency dividing ratio necessary for outputting a desired scale frequency.

Claim 4

A musical scale generating circuit according to claim 2, wherein said frequency dividing ratio being provided from said frequency dividing ratio output circuit is a binary number signal, and wherein said frequency dividing ratio correcting circuit corrects the lowest figure of the binary number signal.

Claim 5

A musical scale generating circuit according to claim 1, wherein said frequency dividing ratio output circuit comprises an address counter and a decoder responsive to an output signal from said address counter for providing said frequency dividing ratio in predetermined order.

Claim 6

In an electronic timepiece having an oscillator and a frequency divider circuit for dividing an output signal from said oscillator, the improvement comprising: a time tone control circuit providing a note length signal and time discriminating signal when discriminating predetermined time; a frequency dividing ratio data output circuit responsive to said note length signal and time discriminating signal for providing a dividing ratio signal; a frequency dividing ratio discriminating circuit responsive to said dividing ratio signal for detecting whether a frequency dividing ratio for providing desired scale frequency is an odd number and providing an output signal; a frequency dividing ratio correcting circuit responsive to said output signal from said frequency dividing ratio discriminating circuit for correcting said dividing ratio signal by one of incrementing and decrementing when an odd-number frequency is detected by said frequency dividing ratio discriminating circuit and providing a corrected signal corresponding to said corrected dividing ratio; a programmable frequency divider responsive to said corrected signal for dividing said clock signal by the dividing ratio being indicated by said corrected signal; an envelope circuit responsive to said note length signal for providing a envelope signal; a mixer for mixing said envelope signal and an output signal of said programmable divider circuit; and a tone generating circuit generating a time tone in response to an output signal of said mixer.

Claim 7

In an electronic timepiece having an oscillator and a frequency divider circuit for dividing an output signal from said oscillator, the improvement comprising: a time tone control circuit providing a note length signal and time discriminating signal when discriminating predetermined time; a frequency dividing ratio data output circuit responsive to said note length signal and time discriminating signal for providing a dividing ratio signal; a frequency dividing ratio discriminating circuit responsive to said dividing ratio signal for detecting whether a frequency dividing ratio for providing desired scale frequency is an odd number and providing an output signal; a frequency dividing ratio correcting circuit responsive to said output signal from said frequency dividing ratio discriminating circuit for correcting said dividing ratio signal by one of incrementing and decrementing when an odd-number frequency is detected by said frequency dividing ratio discriminating circuit and providing a corrected signal corresponding to said corrected dividing ratio; a programmable frequency divider responsive to said corrected signal for dividing said clock signal by the dividing ratio being indicated by said corrected signal; an envelope circuit responsive to said note length signal for providing a envelope signal; a mixer for mixing said envelope signal and an output signal of said programmable divider circuit; and a tone generating circuit generating a time tone in response to an output signal of said mixer.

Claim 8

The improvement according to claim 5, wherein said frequency dividing ratio output circuit comprises an address counter for providing a code signal and a decoder responsive to said code signal for providing said frequency dividing ratio in predetermined order.

Claim 9

The improvement according to claim 5, further comprising a 15-minute counter providing a 15-minute signal every 15 minutes and a 30-minute contact providing a 30-minute signal every 30 minutes.

Claim 10

The improvement according to claim 7, wherein said time tone control circuit is responsive to said 15-minute signal and 30-minute signal for discriminating on the hour, 15 minutes after the hour, 30 minutes after the hour and 45 minutes after the hour, respectively, and for providing said time discriminating signal indicating each of these time.