Patent US4698652A successfully refreshed from Google Patents.
US4698652A
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FET with Fermi level pinning between channel and heavily doped semiconductor gate
Assignee: Hitachi Ltd
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Filing: 1985-05-08
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Granted: 1987-10-06
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Expires: 2005-05-08
Abstract
Abstract Herein disclosed is a semiconductor device in which control means for carriers migrating in a first semiconductor includes an interface state layer lying on the first semiconductor and a second conductor layer lying on the interface state layer. The interface state layer has its Fermi level pinned to that of the second semiconductor layer. By thus constructing an FET or the semiconductor device, an inversion or accumulation layer can be easily formed in the interface merely by applying a voltage to the control means.
Inventors
- 👤 Yasunari Umemoto
- 👤 Susumu Takahashi
- 👤 Yuichi Ono
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:14
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80; H10D30/801; H10D30/803; H10D64/00; H10D64/60; H10D64/602; H10D64/66; H10D64/661; H10D64/667; Y; Y10; Y10S; Y10S148/00; Y10S148/053; Y10S148/072; Y10S148/088; Y10S148/097
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
71 words
A semiconductor device comprising: control means including an interface state layer on a first semiconductor layer having a first type of conductivity, and a second semiconductor layer on said interface state layer, said second semiconductor layer being made of a degenerate semiconductor; and carrier donating and accepting means sandwiching said control means inbetween, said interface state layer having its Fermi level pinned to the Fermi level of said second semiconductor layer.
Claim 2
Dependent Claim
71 words
A semiconductor device comprising: control means including an interface state layer on a first semiconductor layer having a first type of conductivity, and a second semiconductor layer on said interface state layer, said second semiconductor layer being made of a degenerate semiconductor; and carrier donating and accepting means sandwiching said control means inbetween, said interface state layer having its Fermi level pinned to the Fermi level of said second semiconductor layer.
Claim 3
Dependent Claim
35 words
A semiconductor device according to claimm1, wherein said interface state layer has an interface state higher than 10 12 /cm 2 /eV at a position corresponding to the energy gap of said first semiconductor layer.
Claim 4
Dependent Claim
23 words
A semiconductor device according to claim 2, wherein said interface state layer has a thickness within a range of 10 to 30 Å.
Claim 5
Dependent Claim
99 words
A semiconductor device according to claim 1, wherein said second semiconductor layer has an energy band gap larger than the difference between the edge of the energy band of the interface of said first semiconductor layer, in which minority carriers are present, and the edge of the energy band of said second semiconductor layer, in which majority carriers are present, and the same conductivity as that of said first semiconductor layer and there exists a semiconductor layer having the conductivity inverse to that of said first semiconductor layer between said control means and said carrier donating and accepting means.
Claim 6
Dependent Claim
99 words
A semiconductor device according to claim 1, wherein said second semiconductor layer has an energy band gap larger than the difference between the edge of the energy band of the interface of said first semiconductor layer, in which majority carriers are present, and the edge of the energy band of said second semiconductor layer, in which majority carriers are present, and the conductivity inverse to that of said first semiconductor layer, and there exists a semiconductor layer having the same conductivity as that of said first semiconductor layer between said control means and said carrier donating and accepting means.
Claim 7
Dependent Claim
23 words
A semiconductor device according to claim 1, wherein said first semiconductor layer is made of a compound semiconductor belonging to a III-V group.
Claim 8
Dependent Claim
16 words
A semiconductor device according to claim 6, wherein said second semiconductor layer is made of Si.
Claim 9
Dependent Claim
20 words
A semiconductor device according to claim 3, wherein the second semiconductor layer has a thickness of 50 to 5,000 Å.
Claim 10
Dependent Claim
26 words
A semiconductor device according to claim 1, wherein said semiconductor device is a field effect semiconductor device, said control means comprising a gate of the device.
Claim 11
Dependent Claim
46 words
A semiconductor device according to claim 1, wherein the energy band gap of the second semiconductor layer is greater than or equal to the energy difference between the valence band edge of the second semiconductor layer and the conduction band edge of the first semiconductor region.
Claim 12
Dependent Claim
21 words
A semiconductor device according to claim 1, wherein the second semiconductor layer is in direct contact with the interface state layer.
Claim 13
Dependent Claim
23 words
A semiconductor device according to claim 1, wherein said interface state layer has a thickness within a range of 10 to 30 Å.
Claim 14
Dependent Claim
66 words
A semiconductor device comprising: control means including an interface state layer on a first semiconductor layer having a first type of conductivity, and a second semiconductor layer on said interface state layer; and carrier donating and accepting means sandwiching said control means inbetween, said interface state layer being an oxide layer and having its Fermi level pinned to the Fermi level of said second semiconductor layer.
Claim 15
Dependent Claim
66 words
A semiconductor device comprising: control means including an interface state layer on a first semiconductor layer having a first type of conductivity, and a second semiconductor layer on said interface state layer; and carrier donating and accepting means sandwiching said control means inbetween, said interface state layer being an oxide layer and having its Fermi level pinned to the Fermi level of said second semiconductor layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-10-05 | 1991-04-06 | 1991-10-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-10-05 | 1995-04-06 | 1995-10-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-10-05 | 1999-04-06 | 1999-10-06 | $7700.00 | Window Closed / Lapsed |