US4698530A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Power switch for dual power supply circuit
Assignee: National Semiconductor Corp
•
Filing: 1984-11-09
•
Granted: 1987-10-06
•
Expires: 2004-11-09
Abstract
Abstract A power switching circuit 12 for automatically switching between line-driven and battery power supplies 28 and 30 is disclosed. The power switching circuit selectively connects first and second input voltage terminals Vdd and Vbb to an output voltage terminal Vzz. When the line-driven power supply is on, a first transistor Q1 switches on to connect the first input voltage terminal to the output voltage terminal, and a second transistor Q2 switches off to isolate the battery. When the line-driven power supply is off, the first transistor switches off, and the second switches on to connect the battery powered second input voltage terminal to the output voltage terminal.
Inventors
- 👤 Peter K. Thomson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 05:52
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/22; H03K17/223; H02; H02M; H02M1/00; H02M1/10; H03K17/51; H03K17/56; H03K17/687; H03K17/693
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
318 words
A power switching circuit for selectively connecting first and second input voltage terminals to an output voltage terminal, wherein a first input voltage exists between said first input voltage terminal and a reference terminal and a second input voltage exists between said second input voltage terminal and said reference terminal, said circuit comprising: first and second transistors, said first transistor being coupled to connect said first input voltage terminal to said output voltage terminal and having a gate terminal, said second transistor being coupled to connect said second input voltage terminal to said output voltage terminal and having a gate terminal; and switching means coupled to respond to the voltage at said first input voltage terminal for controlling the conduction in said first and second transistors, said switching means being operable for turning said first transistor on and said second transistor off when the magnitude of said first input voltage exceeds a predetermined value and for turning said first transistor off and said second transistor on when the magnitude of said first input voltage does not exceed said predetermined value, and including first and second inverters, said first inverter having an output terminal coupled to said gate of said second transistor said second inverter having an input terminal coupled to said output terminal of said first inverter and having an output terminal coupled to said gate terminal of said first transistor, said first inverter also having an input terminal coupled to said output voltage terminal through first resistor means and coupled to said reference terminal through a third transistor, said third transistor having a gate terminal coupled to said reference terminal through second resistor means and coupled to said first voltage input terminal through a fourth transistor, said fourth transistor having a gate terminal with a reference voltage applied thereto and operable for switching off when the magnitude of said input voltage does not exceed said predetermined value.
Claim 2
Dependent Claim
318 words
A power switching circuit for selectively connecting first and second input voltage terminals to an output voltage terminal, wherein a first input voltage exists between said first input voltage terminal and a reference terminal and a second input voltage exists between said second input voltage terminal and said reference terminal, said circuit comprising: first and second transistors, said first transistor being coupled to connect said first input voltage terminal to said output voltage terminal and having a gate terminal, said second transistor being coupled to connect said second input voltage terminal to said output voltage terminal and having a gate terminal; and switching means coupled to respond to the voltage at said first input voltage terminal for controlling the conduction in said first and second transistors, said switching means being operable for turning said first transistor on and said second transistor off when the magnitude of said first input voltage exceeds a predetermined value and for turning said first transistor off and said second transistor on when the magnitude of said first input voltage does not exceed said predetermined value, and including first and second inverters, said first inverter having an output terminal coupled to said gate of said second transistor said second inverter having an input terminal coupled to said output terminal of said first inverter and having an output terminal coupled to said gate terminal of said first transistor, said first inverter also having an input terminal coupled to said output voltage terminal through first resistor means and coupled to said reference terminal through a third transistor, said third transistor having a gate terminal coupled to said reference terminal through second resistor means and coupled to said first voltage input terminal through a fourth transistor, said fourth transistor having a gate terminal with a reference voltage applied thereto and operable for switching off when the magnitude of said input voltage does not exceed said predetermined value.
Claim 3
Dependent Claim
49 words
A circuit as recited in claim 1 and having said output voltage terminal at a higher voltage than said reference voltage terminal, wherein said first, second, and fourth transistors are p-channel enhancement mode field effect transistors, and wherein said third transistor is an n-channel enhancement mode field effect transistor.
Claim 4
Dependent Claim
51 words
A circuit as recited in claim 1 wherein said reference voltage is provided by a fifth transistor and a diode coupled in series between said gate terminal of said fourth transistor and said second input voltage terminal and by a sixth transistor coupled between said gate terminal and said reference terminal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-10-05 | 1991-04-06 | 1991-10-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-10-05 | 1995-04-06 | 1995-10-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-10-05 | 1999-04-06 | 1999-10-06 | $7700.00 | Window Closed / Lapsed |