Logic circuit having testability for defective via contacts

Claim 1

An integrated circuit having improved testability for defective via contacts, comprising: a plurality of N logic gages which are in a semiconductor chip; one of said gates having an output terminal which is connected by a conductor in said chip to respective input terminals on the remaining N-1 logic gates; said one logic gate having ON and OFF states which respectively couple and decouple at 1 voltage level to said conductor; a first resistor means, having a resistance R1, which couples said conductor through a first via contact, in the absence of a defect therein, to a 0 voltage bus; said remaining N-1 logic gates being constructed such that they each drain a current I b from said conductor through their respective input terminal; and a second resistor means, having a resistance R2, which couples said conductor through a second via contact, in the absence of a defect therein, to another voltage bus; said resistance R2 being selected to (a) carry a current of magnitude I b (N-1) from said another volage bus to said conductor under the condition where said first via is open due to a defect and said one logic gate is OFF, (b) produce a voltage drop when said current of magnitude I b (N-1) is flowing such that the voltage coupled to said conductor is closer to said 1 voltage than to said 0 voltage, and (c) be substantially larger than said resistance R1.