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Patent US4694564A successfully refreshed from Google Patents.
US4694564A
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US
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Method for the manufacture of a Schottky gate field effect transistor
Assignee: NTT Inc
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Filing: 1986-07-21
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Granted: 1987-09-22
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Expires: 2006-07-21
Abstract
Abstract In the manufacture of a Schottky gate field effect transistor, an insulating film is deposited on the main surface of a semiconductor substrate and is then selectively removed to form therein a window through which the substrate surface region for forming an active layer is exposed to a space in which the gate will ultimately be provided. A metal which forms a Schottky junction between it and the semiconductor of the active layer and can be removed by anisotropic etching and a metal which can be used as a mask for the etching of the above metal are deposited in layers on the insulating film and the substrate surface exposed through the window. The overlying metal layer thus deposited is planarized to leave in the window alone. The underlying metal layer is selectively removed by anisotropic etching through the overlying metal layer remaining in the window, thus forming a gate electrode made up of the overlying and underlying metal layers. The structure thus obtained is small in the overlapping of the gate electrode on the adjoining insulating films, ensuring the reduction of parasitic capacitances to thereby speed up the operation of the device.
Inventors
- 👤 Takatomo Enoki
- 👤 Kimiyoshi Yamasaki
- 👤 Kuniki Ohwada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 10:40
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/061; H10D30/0612; H10D30/0614; H10D64/00; H10D64/01; H10D64/012; H10D64/0124; H10D64/0125; Y; Y10; Y10S; Y10S148/00; Y10S148/139
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
247 words
A method for the manufacture of a field effect transistor, comprising: a step wherein a source region, a drain region, and an active region sandwiched therebetween are formed in the body of a semiconductor substrate near its one main surface and an insulating film of at least one layer deposited all over the main surface of the substrate is selectively removed, exposing a part of the active region formed in the semiconductor substrate; a step wherein an underlying metal which forms a Schottky junction between it and the semiconductor of the active region and can be removed by anisotropic etching and an overlying metal of at least one layer which is capable of serving as a mask for the etching of the underlying metal are deposited in layers on the insulating film and the substrate surface exposed through the aperture made in the insulating film, filling the aperture with the underlying and the overlying metal; as step wherein the surface of the overlying metal layer is planarized so that the overlying metal layer selectively remains in the aperture of the insulating film; a step wherein the underlying metal layer is selectively removed by anisotropic etching through the remaining the overlying metal, forming a gate electrode of the overlying and underlying metal layers on the active region exposed through the aperture of the insulating film; and a step wherein the insulating film is partly removed and source and drain electrodes are formed on the source drain regions, respectively.
Claim 2
Independent Claim
247 words
A method for the manufacture of a field effect transistor, comprising: a step wherein a source region, a drain region, and an active region sandwiched therebetween are formed in the body of a semiconductor substrate near its one main surface and an insulating film of at least one layer deposited all over the main surface of the substrate is selectively removed, exposing a part of the active region formed in the semiconductor substrate; a step wherein an underlying metal which forms a Schottky junction between it and the semiconductor of the active region and can be removed by anisotropic etching and an overlying metal of at least one layer which is capable of serving as a mask for the etching of the underlying metal are deposited in layers on the insulating film and the substrate surface exposed through the aperture made in the insulating film, filling the aperture with the underlying and the overlying metal; as step wherein the surface of the overlying metal layer is planarized so that the overlying metal layer selectively remains in the aperture of the insulating film; a step wherein the underlying metal layer is selectively removed by anisotropic etching through the remaining the overlying metal, forming a gate electrode of the overlying and underlying metal layers on the active region exposed through the aperture of the insulating film; and a step wherein the insulating film is partly removed and source and drain electrodes are formed on the source drain regions, respectively.
Claim 3
Dependent Claim
36 words
The manufacturing method according to claim 1 wherein the thickness of the overlying metal layer is controlled so as to control the width of the overlying metal layer remaining in the aperture of the insulating film.
Claim 4
Dependent Claim
27 words
The manufacturing method according to claim 1 wherein after the planarization of the overlying metal layer its surface is futher over-etched to back its upper marginal edges.
Claim 5
Dependent Claim
126 words
The manufacturing method according to claim 1 further including a step wherein a multi-level resist layer is formed on one main surface of the semiconductor substrate and patterned to expose the surface regions of the semiconductor substrate where the source and drain regions will ultimately be formed, an impurity which will form the source and drain regions is ion implanted using the multi-level resist layer as a mask, an insulating film is deposited on the main surface of the semiconductor substrate, and the insulating film overlying the multi-level resist layer is lifted off together with the latter, thereby leaving on the main surface of the semiconductor substrate the insulating surface in a pattern inverted from that of the lowermost resist film of the multi-level resist layer.
Claim 6
Dependent Claim
29 words
The manufacturing method according to claim 4 wherein overhanging portions of the multi-level resist layer are removed after the ion implantation of the impurity through the muli-level resist layer.
Claim 7
Dependent Claim
25 words
The manufacturing method according to claim 1 wherein the underlying metal layer is formed of molybdenum (Mo), tantalum (Ta), tungsten silicide, or tungsten silicon nitride.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-09-21 | 1991-03-23 | 1991-09-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-09-21 | 1995-03-23 | 1995-09-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-09-21 | 1999-03-23 | 1999-09-22 | $7700.00 | Window Closed / Lapsed |