US4694451A
Expired / Lapsed
US
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Adaptive digital filter
Assignee: British Telecommunications PLC
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Filing: 1985-01-10
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Granted: 1987-09-15
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Expires: 2005-01-10
Abstract
Abstract A digital filter comprises a plurality of delay stages 41 such as shift register stages through which an input x(t) is fed. Each of a plurality of individually addressable random access memories 42 is addressed by the output of one of the delay stages and the output from the RAMs 42 are combined. An error signal adapts the values stored within the RAMs. The filter may also be extended such that each RAM receives an address input from more than one delay stage.
Inventors
- 👤 Peter F. Adams
- 👤 Colin F. N. Cowan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:29
CPC Classifications
H; H03; H03H; H03H21/00; H03H21/0012; H03H17/00; H03H17/02; H03H17/06; H03H17/0607; H04; H04B; H04B3/00; H04B3/02; H04B3/20; H04B3/23; H04B3/231; H04B3/238
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
124 words
A digital filter comprising: a plurality of delay stages for receiving, delaying and then outputting an input digital signal, a plurality of individually addressable random access memory devices for storing respective data values therein, means for addressing and accessing stored data values in each of said memory devices, said means for addressing and accessing each said memory device being connected to receive the output from at least two of said delay stages, means for combining the thus addressed outputs read from said memory devices to provide a filter output signal, and means for processing the filter output signal to provide an error signal which may be used to adapt the data values stored within said memory devices so as to minimize said error signal.
Claim 2
Dependent Claim
124 words
A digital filter comprising: a plurality of delay stages for receiving, delaying and then outputting an input digital signal, a plurality of individually addressable random access memory devices for storing respective data values therein, means for addressing and accessing stored data values in each of said memory devices, said means for addressing and accessing each said memory device being connected to receive the output from at least two of said delay stages, means for combining the thus addressed outputs read from said memory devices to provide a filter output signal, and means for processing the filter output signal to provide an error signal which may be used to adapt the data values stored within said memory devices so as to minimize said error signal.
Claim 3
Dependent Claim
24 words
A digital filter according to claim 1 in which each memory device is addressed by the output from the same number of delay stages.
Claim 4
Dependent Claim
21 words
A digital filter according to claim 1 in which each memory device is addressed by the output from adjacent delay stages.
Claim 5
Dependent Claim
35 words
A transmitter/receiver unit including a digital filter according to claim 1 in which said filter output signal forms an echo copy signal for cancelling noise at the receiver due to an output from the transmitter.
Claim 6
Dependent Claim
25 words
A transmitter/receiver unit according to claim 4 wherein each random access memory of the digital filter is addressed by a plurality of adjacent delay stages.
Claim 7
Dependent Claim
88 words
A digital filtering method comprising the steps of: receiving a digital input signal x(t) and delaying it to provide a succession of delayed versions thereof x(t-T), x(t-2T), x(t-3T) . . . , where T is a predetermined time period, using at least two of such signals x(t), x(t-T), x(T-2T), x(t-3T) . . . to address stored data values in RAM and to provide a plurality of addressed RAM outputs; and combining said addressed RAM outputs to provide a digitally filtered output representation y(t) of said input signal x(t).
Claim 8
Dependent Claim
88 words
A digital filtering method comprising the steps of: receiving a digital input signal x(t) and delaying it to provide a succession of delayed versions thereof x(t-T), x(t-2T), x(t-3T) . . . , where T is a predetermined time period, using at least two of such signals x(t), x(t-T), x(T-2T), x(t-3T) . . . to address stored data values in RAM and to provide a plurality of addressed RAM outputs; and combining said addressed RAM outputs to provide a digitally filtered output representation y(t) of said input signal x(t).
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-09-14 | 1991-03-16 | 1991-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-09-14 | 1995-03-16 | 1995-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-09-14 | 1999-03-16 | 1999-09-15 | $7700.00 | Window Closed / Lapsed |