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US4694427A
Expired / Lapsed
US
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Programmable semiconductor memory device with combined sense amplification and programming capability
Assignee: Toshiba Corp
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Filing: 1985-07-26
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Granted: 1987-09-15
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Expires: 2005-07-26
Abstract
Abstract A semiconductor memory device provided with first and second bit lines, each of which is connected to a memory cell comprising a nonvolatile transistor and a dummy cell comprising a nonvolatile transistor. The first and second bit lines are respectively connected to high voltage generators which are applied at the time of data programming. At the time of data reading, data-detecting and storing means comprising a flip-flop circuit detects data, while amplifying a potential difference between the first and second bit lines. At the time of data writing, the data detecting and storing means temporarily stores data in accordance with the contents of externally supplied writing data. A first switching transistor is provided between the first data input-output node of the data-detecting and storing means and the first bit line. The second switching transistor is connected between the second data input-output node of the data-detecting and storing means and second bit line. The paired switching transistors are controlled in accordance with the operation mode of the memory device.
Inventors
- 👤 Junichi Miyamoto
- 👤 Jun-ichi Tsujimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 19:49
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C16/28
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
436 words
A programmable semiconductor memory device for storing input data comprising: a first bit line connected to first memory cells, each comprising a nonvolatile transistor for storing data, and a first dummy cell also comprising a nonvolatile transistor; a second bit line connected to second memory cells, each comprising a nonvolatile transistor for storing data, and a second dummy cell also comprising a nonvolatile transistor; high voltage generation means, connected to said first and second bit lines, for providing high voltage programming data for storage of said input data into said first and second memory cells and for erasing data from said first and second memory cells; data detecting and storing means for amplifying a potential difference between said first and second bit lines caused when one of said or first memory cells is selected and for temporarily holding data prior to storage into said first and second memory cells, the amplified potential difference between said first and second bit lines reflecting data stored in said selected one of said first or second memory cells, and said data detecting and storing means including a flip-flop having two input/output nodes; first switching means, connected between said first bit line and said first input/output node of said data detecting and storing means flip-flop for connecting said flip-flop to said first bit line in response to an enable signal; second switching means, connected between said second bit line and said second input/output node of said data detecting and storing means flip-flop, for connecting said flip-flop to said second bit line in response to said enable signal; signal compensation means for selectively inverting the level of said amplified potential difference according to whether said selected memory cell is connected to said first bit line or said second bit line; and data storage controlling means for controlling the storage of said input data into said first and second memory cells, said data storage controlling means comprising a first switching transistor having a gate receiving a first storage signal and having a current path connected between a predetermined potential and said first input/output node of said data detecting and storage means flip-flop, a second switching transistor having a gate receiving a second storage signal and having a current path connected between said predetermined potential and said input/output node of said data detecting and storing means flip-flop, and input data decoding means, coupled to the gates of said first and second transistors, for decoding said input data into said first storage signal having the same level as said input data and said second storage signal having a complementary level to said first storage signal.
Claim 2
Dependent Claim
436 words
A programmable semiconductor memory device for storing input data comprising: a first bit line connected to first memory cells, each comprising a nonvolatile transistor for storing data, and a first dummy cell also comprising a nonvolatile transistor; a second bit line connected to second memory cells, each comprising a nonvolatile transistor for storing data, and a second dummy cell also comprising a nonvolatile transistor; high voltage generation means, connected to said first and second bit lines, for providing high voltage programming data for storage of said input data into said first and second memory cells and for erasing data from said first and second memory cells; data detecting and storing means for amplifying a potential difference between said first and second bit lines caused when one of said or first memory cells is selected and for temporarily holding data prior to storage into said first and second memory cells, the amplified potential difference between said first and second bit lines reflecting data stored in said selected one of said first or second memory cells, and said data detecting and storing means including a flip-flop having two input/output nodes; first switching means, connected between said first bit line and said first input/output node of said data detecting and storing means flip-flop for connecting said flip-flop to said first bit line in response to an enable signal; second switching means, connected between said second bit line and said second input/output node of said data detecting and storing means flip-flop, for connecting said flip-flop to said second bit line in response to said enable signal; signal compensation means for selectively inverting the level of said amplified potential difference according to whether said selected memory cell is connected to said first bit line or said second bit line; and data storage controlling means for controlling the storage of said input data into said first and second memory cells, said data storage controlling means comprising a first switching transistor having a gate receiving a first storage signal and having a current path connected between a predetermined potential and said first input/output node of said data detecting and storage means flip-flop, a second switching transistor having a gate receiving a second storage signal and having a current path connected between said predetermined potential and said input/output node of said data detecting and storing means flip-flop, and input data decoding means, coupled to the gates of said first and second transistors, for decoding said input data into said first storage signal having the same level as said input data and said second storage signal having a complementary level to said first storage signal.
Claim 3
Dependent Claim
46 words
The programmable semiconductor memory device of claim 1 wherein said first and second switching means include third and fourth switching transistors, respectively, which are rendered conductive by said enable signal when said data from said memory cell is amplified by said data detecting and storing means.
Claim 4
Dependent Claim
38 words
The programmable semiconductor memory device according to claim 1 wherein said first and second switching means include third and fourth transistors, respectively, which are rendered conductive for storing said input data into said first and second memory cells.
Claim 5
Dependent Claim
37 words
The semiconductor memory device of claim 1 wherein said first and second means include third and fourth switching transistors, respectively, which are rendered nonconductive by said enable signal when said first and second memory cells are erased.
Claim 6
Dependent Claim
35 words
The semiconductor memory device according to claim 1, further comprising a plurality of additional individual bit lines and wherein said data-detecting and storing means comprises a single circuit connected to all of said bit lines.
Claim 7
Dependent Claim
29 words
The semiconductor memory device according to claim 1 wherein each said first and second memory cell comprises a data-storing nonvolatile transistor and selection transistor for specifying said nonvolatile transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-09-14 | 1991-03-16 | 1991-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-09-14 | 1995-03-16 | 1995-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-09-14 | 1999-03-16 | 1999-09-15 | $7700.00 | Window Closed / Lapsed |