Patent US4694277A successfully refreshed from Google Patents.
US4694277A
Expired / Lapsed
US
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A/D converter
Assignee: NEC Electronics Corp
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Filing: 1986-02-21
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Granted: 1987-09-15
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Expires: 2006-02-21
Abstract
Abstract A dual slope A/D converter with a zero compensation circuit includes a single power source, an integrator, and a MOS switch constituting the zero compensation circuit and adapted to apply an output voltage to the noninverting input terminal of an operational amplifier constituting the integrator for a zero compensation duration. The A/D converter further includes an amplifier and a MOS transistor with the same characteristics as those of the MOS switch. The gate and source of the MOS transistor are connected to the noninverting input terminal of the operational amplifier. The amplifier doubles a voltage at the noninverting input terminal of the operational amplifier. A doubled voltage is applied to the drain of the MOS transistor.
Inventors
- 👤 Akinori Takahashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:37
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/10; H03M1/1009; H03M1/1014; H03M1/12; H03M1/50; H03M1/52
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
227 words
An A/D converter with an automatic zero compensation circuit, comprising: a predetermined voltage; an integrator for receiving as input signals the predetermined voltage in a first step of A/D conversion, a difference between the predetermined voltage and an analog voltage to be A/D converted in a second step, a sum of the predetermined voltage and a reference voltage in a third step, the input signals being supplied to an inverting input terminal of an operational amplifier constituting said integrator, a noninverting input terminal of said operational amplifier being connected to one terminal of a capacitor, and the other terminal of said capacitor being grounded; a comparator for comparing the predetermined voltage with an output voltage from said integrator and for generating a coincidence signal representing a coincidence between the two signals; and an automatic zero compensation circuit connected to an output terminal of said comparator only for a duration of the first step, said automatic zero compensation circuit including: a first MOS transistor coupled between said output terminal of said comparator and said one terminal of said capacitor; an amplifier for substantially doubling a voltage at said one terminal of said capacitor; and a second MOS transistor which has the same physical configuration as said first MOS transistor and is coupled between said noninverting input terminal of said operational amplifier and an output terminal of said amplifier.
Claim 2
Dependent Claim
227 words
An A/D converter with an automatic zero compensation circuit, comprising: a predetermined voltage; an integrator for receiving as input signals the predetermined voltage in a first step of A/D conversion, a difference between the predetermined voltage and an analog voltage to be A/D converted in a second step, a sum of the predetermined voltage and a reference voltage in a third step, the input signals being supplied to an inverting input terminal of an operational amplifier constituting said integrator, a noninverting input terminal of said operational amplifier being connected to one terminal of a capacitor, and the other terminal of said capacitor being grounded; a comparator for comparing the predetermined voltage with an output voltage from said integrator and for generating a coincidence signal representing a coincidence between the two signals; and an automatic zero compensation circuit connected to an output terminal of said comparator only for a duration of the first step, said automatic zero compensation circuit including: a first MOS transistor coupled between said output terminal of said comparator and said one terminal of said capacitor; an amplifier for substantially doubling a voltage at said one terminal of said capacitor; and a second MOS transistor which has the same physical configuration as said first MOS transistor and is coupled between said noninverting input terminal of said operational amplifier and an output terminal of said amplifier.
Claim 3
Dependent Claim
63 words
A converter according to claim 1, further comprising control means for controlling durations of the first to third steps of A/D conversion and for generating a signal representing the duration of the third step in response to the coincidence signal from said comparator; and counter and latch means for counting an output signal from said control means and generating an A/D-converted digital output.
Claim 4
Dependent Claim
69 words
A converter according to claim 1, wherein said amplifier includes an operational amplifier, a noninverting input terminal of which is connected to said one terminal of said capacitor, a first resistor being connected between an inverting input terminal and an output terminal of said operational amplifier, and a second resistor with the same resistance as that of said first resistor being connected between said inverting input terminal and ground.
Claim 5
Dependent Claim
301 words
An A/D converter with an automatic zero compensation circuit, comprising: a predetermined voltage; an integrator for receiving as input signals the predetermined voltage in a first step of A/D conversion, a difference between the predetermined voltage and an analog voltage to be A/D converted in a second step, a sum of the predetermined voltage and a reference voltage in a third step, the input signals being supplied to an inverting input terminal of a first operational amplifier constituting said integrator, a noninverting input terminal of said first operational amplifier being connected to one terminal of a capacitor, and the other terminal of said capacitor being grounded; a comparator for comparing the predetermined voltage with an output voltage from said integrator and for generating a coincidence signal representing a coincidence between the two signals; and an automatic zero compensation circuit connected to an output terminal of said comparator only for a duration of the first step, said automatic zero compensation circuit including: a first MOS transistor coupled between said output terminal of said comparator and said one terminal of said capacitor; an amplifier for generating a voltage proportional to a potential at said one terminal of said capacitor, said amplifier including a second operational amplifier, a noninverting input terminal of which is connected to said one terminal of said capacitor, a first resistor being connected between an inverting input terminal and an output terminal of said second operational amplifier, and a second resistor with the same resistance as that of said first resistor being connected between said inverting input terminal of said second operational amplifier and ground; and a second MOS transistor which has the same physical configuration as said first MOS transistor and is coupled between said noninverting input terminal of said operational amplifier and an output terminal of said amplifier.
Claim 6
Dependent Claim
301 words
An A/D converter with an automatic zero compensation circuit, comprising: a predetermined voltage; an integrator for receiving as input signals the predetermined voltage in a first step of A/D conversion, a difference between the predetermined voltage and an analog voltage to be A/D converted in a second step, a sum of the predetermined voltage and a reference voltage in a third step, the input signals being supplied to an inverting input terminal of a first operational amplifier constituting said integrator, a noninverting input terminal of said first operational amplifier being connected to one terminal of a capacitor, and the other terminal of said capacitor being grounded; a comparator for comparing the predetermined voltage with an output voltage from said integrator and for generating a coincidence signal representing a coincidence between the two signals; and an automatic zero compensation circuit connected to an output terminal of said comparator only for a duration of the first step, said automatic zero compensation circuit including: a first MOS transistor coupled between said output terminal of said comparator and said one terminal of said capacitor; an amplifier for generating a voltage proportional to a potential at said one terminal of said capacitor, said amplifier including a second operational amplifier, a noninverting input terminal of which is connected to said one terminal of said capacitor, a first resistor being connected between an inverting input terminal and an output terminal of said second operational amplifier, and a second resistor with the same resistance as that of said first resistor being connected between said inverting input terminal of said second operational amplifier and ground; and a second MOS transistor which has the same physical configuration as said first MOS transistor and is coupled between said noninverting input terminal of said operational amplifier and an output terminal of said amplifier.
Claim 7
Dependent Claim
268 words
An A/D converter with an automatic zero compensation circuit, comprising: a predetermined voltage; an integrator for receiving as input signals the predetermined voltage in a first step of A/D conversion, a difference between the predetermined voltage and an analog voltage to be A/D converted in a second step, a sum of the predetermined voltage and a reference voltage in a third step, the input signals being supplied to an inverting input terminal of a first operational amplifier constituting said integrator, a noninverting input terminal of said first operational amplifier being connected to one terminal of a capacitor, and the other terminal of said capacitor being grounded; a comparator for comparing the predetermined voltage with an output voltage from said integrator and for generating a coincidence signal representing a coincidence between the two signals; and an automatic zero compensation circuit connected to an output terminal of said comparator only for a duration of the first step, said automatic zero compensation circuit including: a first MOS transistor coupled between said output terminal of said comparator and said one terminal of said capacitor; an amplifier for generating a voltage proportional to a potential at said one terminal of said capacitor; and a second MOS transistor which has the same physical configuration as said first MOS transistor and is coupled between said noninverting input terminal of said first operational amplifier and an output terminal of said amplifier, whereby said second MOS transistor and said amplifier cooperate with each other to compensate a leakage current to said first MOS transistor in order to maintain the potential at said one terminal of said capacitor.
Claim 8
Dependent Claim
268 words
An A/D converter with an automatic zero compensation circuit, comprising: a predetermined voltage; an integrator for receiving as input signals the predetermined voltage in a first step of A/D conversion, a difference between the predetermined voltage and an analog voltage to be A/D converted in a second step, a sum of the predetermined voltage and a reference voltage in a third step, the input signals being supplied to an inverting input terminal of a first operational amplifier constituting said integrator, a noninverting input terminal of said first operational amplifier being connected to one terminal of a capacitor, and the other terminal of said capacitor being grounded; a comparator for comparing the predetermined voltage with an output voltage from said integrator and for generating a coincidence signal representing a coincidence between the two signals; and an automatic zero compensation circuit connected to an output terminal of said comparator only for a duration of the first step, said automatic zero compensation circuit including: a first MOS transistor coupled between said output terminal of said comparator and said one terminal of said capacitor; an amplifier for generating a voltage proportional to a potential at said one terminal of said capacitor; and a second MOS transistor which has the same physical configuration as said first MOS transistor and is coupled between said noninverting input terminal of said first operational amplifier and an output terminal of said amplifier, whereby said second MOS transistor and said amplifier cooperate with each other to compensate a leakage current to said first MOS transistor in order to maintain the potential at said one terminal of said capacitor.
Claim 9
Dependent Claim
63 words
A converter according to claim 5, further comprising control means for controlling durations of the first to third steps of A/D conversion and for generating a signal representing the duration of the third step in response to the coincidence signal from said comparator; and counter and latch means for counting an output signal from said control means and generating an A/D-converted digital output.
Claim 10
Dependent Claim
75 words
A converter according to claim 5, wherein said amplifier includes a second operational amplifier, a noninverting input terminal of which is connected to said one terminal of said capacitor; a first being connected between an inverting input terminal and an output terminal of said second operational amplifier; and a second resistor with the same resistance as that of said first resistor being connected between said inverting input terminal of said second operational amplifier and ground.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-09-14 | 1991-03-16 | 1991-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-09-14 | 1995-03-16 | 1995-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-09-14 | 1999-03-16 | 1999-09-15 | $7700.00 | Window Closed / Lapsed |