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US4694201A Expired / Lapsed US ⏱️ 0.0 years remaining

Current-saving CMOS input buffer

Assignee: Motorola Solutions Inc
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Filing: 1985-04-30
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Granted: 1987-09-15
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Expires: 2005-04-30
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Abstract

Abstract A current-saving CMOS signal input buffer is provided, having at least two CMOS output transistors (each having an input) connected in complementary fashion with a common output taken therebetween, complementary current mirrors coupled to the output transistor inputs, an input signal capacitively coupled to at least one of the output transistor inputs, a reference impedance coupled between the complementary current mirrors, and isolation impedances coupled between the complementary current mirrors and the output transistor inputs.

Inventors

  • 👤 Barry L. Jason

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 07:19
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 121 words
A current saving CMOS signal buffer comprising: input means for receiving an input signal; output means for providing an output signal; at least two CMOS output transistors connected in a push-pull configuration between a supply voltage differential comprising a positive supply voltge and a negative supply voltage said CMOS output transistors having their gates connected in common to said input means and wherein a common output between said transistors connects to said output means; means coupled to said two CMOS output transistors forming first and second current mirrors for providing a source of substantially constant current mirrored to said output transistors; and such that current flows through said output transistors to increase substantially linearly as said supply voltage differential increases linearly.
Claim 2
Dependent Claim 121 words
A current saving CMOS signal buffer comprising: input means for receiving an input signal; output means for providing an output signal; at least two CMOS output transistors connected in a push-pull configuration between a supply voltage differential comprising a positive supply voltge and a negative supply voltage said CMOS output transistors having their gates connected in common to said input means and wherein a common output between said transistors connects to said output means; means coupled to said two CMOS output transistors forming first and second current mirrors for providing a source of substantially constant current mirrored to said output transistors; and such that current flows through said output transistors to increase substantially linearly as said supply voltage differential increases linearly.
Claim 3
Dependent Claim 17 words
The buffer of claim 1 wherein an impedance is coupled between said first and second current mirrors.
Claim 4
Dependent Claim 30 words
The buffer of claim 1 and further including isolation means for providing an impedance between said means for providing a source of substantially constant current means and said output transistors.
Claim 5
Dependent Claim 27 words
The buffer of claim 3 wherein: said isolation means includes first and second transistors coupled between said first and second current mirrors and said output transistors, respectively.
Claim 6
Dependent Claim 22 words
The buffer of claim 1 and further including a capacitor coupled between said input means and only one of said output transistors.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1990-09-14 1991-03-16 1991-09-15 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1994-09-14 1995-03-16 1995-09-15 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1998-09-14 1999-03-16 1999-09-15 $7700.00 Window Closed / Lapsed

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