Patent US4694200A successfully refreshed from Google Patents.
US4694200A
Expired / Lapsed
US
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Device for detecting a pulse train in noise and application to a radionavigation aid system of DME type
Assignee: Thales SA
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Filing: 1986-02-25
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Granted: 1987-09-15
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Expires: 2006-02-25
Abstract
Abstract A device for detecting, among noise, each of the pulses of a pulse train, comprising essentially: a detector detecting the peak of a pulse; a first delay line; a first comparator comparing the level of the first delayed pulse with the half peak value; a second delay line for delaying the pulse train with a second delay different from the first one; a second comparator comparing the signal delivered by a second delay line with the signal delivered by the first delay line and with the half peak value, and an AND gate delivering an output signal when there is coincidence of the output signals from said two comparators.
Inventors
- 👤 Joseph Hetyei
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 11:49
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/153; H03K5/1532; G; G01; G01S; G01S13/00; G01S13/02; G01S13/06; G01S13/08; G01S13/10; G01S13/14; G01S13/74; G01S13/76; G01S13/78; G01S13/785
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
229 words
A device for detecting a pulse train, said train comprising a plurality of pulses, said device comprising: means for detecting the peak value of the first pulse of said train; first analog delay means receiving said pulse train and conferring thereon a first delay for forming a first output signal; a first comparator for comparing the level of said first output signal with the half of said peak value and delivering a first signal when said first output signal becomes equal to said half peak value and as long as said first output signal remains greater than said half peak value; second analog delay means receiving said pulse train, conferring thereon a second delay, different from said first delay for forming a second output signal; a second comparator comparing the level of said second output signal with said half peak value and with said first output signal and delivering a second signal when said second output signal becomes equal either to said half value or to said first output signal, and delivering said second signal from the second comparator as long as said second output signal remains greater than the greatest of said half value and said first output signal; logic means receiving said first and second signals from said first and second comparators respectively and delivering a signal when there is coincidence between said first and second signals.
Claim 2
Independent Claim
229 words
A device for detecting a pulse train, said train comprising a plurality of pulses, said device comprising: means for detecting the peak value of the first pulse of said train; first analog delay means receiving said pulse train and conferring thereon a first delay for forming a first output signal; a first comparator for comparing the level of said first output signal with the half of said peak value and delivering a first signal when said first output signal becomes equal to said half peak value and as long as said first output signal remains greater than said half peak value; second analog delay means receiving said pulse train, conferring thereon a second delay, different from said first delay for forming a second output signal; a second comparator comparing the level of said second output signal with said half peak value and with said first output signal and delivering a second signal when said second output signal becomes equal either to said half value or to said first output signal, and delivering said second signal from the second comparator as long as said second output signal remains greater than the greatest of said half value and said first output signal; logic means receiving said first and second signals from said first and second comparators respectively and delivering a signal when there is coincidence between said first and second signals.
Claim 3
Dependent Claim
17 words
The device as claimed in claim 1, wherein said second delay is smaller than said first delay.
Claim 4
Dependent Claim
57 words
The device as claimed in claim 2, further comprising third delay means conferring a third delay on said second signal from said second comparator, said third delay being less than the difference between said first and second delays, but close to this difference, said third delay means being positioned between said second comparator and said logic means.
Claim 5
Dependent Claim
15 words
The device as claimed in claim 1, wherein said logic means comprise an AND gate.
Claim 6
Dependent Claim
15 words
The device as claimed in claim 3, wherein said third delay means comprise a monostable.
Claim 7
Dependent Claim
86 words
The device as claimed in claim 1, wherein said detection means comprise: a differential amplifier having two inputs, receiving the pulse train at its first input (+); a diode connected by its anode to the output of said amplifier; a capacitor connected between the cathode of said diode and ground; a transistor whose base is connected to said cathode, collector to an electric power supply and emitter to the second input of said amplifier, the peak value of said pulse train being available at said emitter.
Claim 8
Dependent Claim
42 words
The device as claimed in claim 1, wherein said first delay means comprise a delay line of the LC type at the ends of which are connected respectively two resistors each having an impedance equal to the characteristic impedance of said line.
Claim 9
Dependent Claim
42 words
The device as claimed in claim 1, wherein said second delay means comprise a delay line of the LC type at the ends of which are connected respectively two resistors each having an impedance equal to the characteristic impedance of said line.
Claim 10
Dependent Claim
30 words
The device as claimed in claim 1, further comprising decoupling means receiving said pulse train and transmitting it to said detection means and to said first and second delay means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-09-14 | 1991-03-16 | 1991-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-09-14 | 1995-03-16 | 1995-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-09-14 | 1999-03-16 | 1999-09-15 | $7700.00 | Window Closed / Lapsed |