Patent US4692931A successfully refreshed from Google Patents.
US4692931A
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US
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Synchronization circuit capable of establishing synchronism even when a sampling rate is invariable
Assignee: NEC Corp
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Filing: 1985-10-30
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Granted: 1987-09-08
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Expires: 2005-10-30
Abstract
Abstract In a synchronization circuit for use in demodulating an input signal carrying a transmission data signal at a symbol rate, a sampling circuit samples the input signal at a predetermined sample rate which may be different from the symbol rate, to produce a sequence of sampled signals. The sampled signal sequence is interpolated by the use of an interpolator into first and second partial interpolated signals which have different phases from each other. The first and second partial interpolated signals are processed by a processing circuit to produce timing errors between the first partial interpolated signals and the sampled signal sequence. The processing circuit controls the phases of the first and second partial interpolated signals with reference to the timing errors so that the both partial interpolated signals are derived at predetermined points of the sampled signal sequence. On reception of the transmission data signal of a multi-level divisible into a plurality of bits, the interpolator comprises a plurality of elementary interpolators for interpolating the respective bits to produce fragmentary interpolated signals. The fragmentary interpolated signals are combined into the interpolated signal sequence. The elementary interpolators may be controlled by two internal samplers in consideration of the timing errors.
Inventors
- 👤 Tomoki Ohsawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 15:37
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/0016; H04L7/002; H04L7/0029; H04L7/02; H04L7/033; H04L7/0334
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
313 words
A synchronization circuit responsive to an input signal carrying a transmission data signal and being received at a transmission rate for producing an output signal which is representative of reproductions of said transmission data signal, said circuit comprising: sampling means responsive to said input signal for sampling it at a predetermined sample rate to produce a sequence of sampled signals at said predetermined sample rate; interpolating means coupled to said sampling means for interpolating said sampled signal sequence to produce an interpolated signal sequence; and processing means coupled to said interpolating means for processing said interpolated signal sequence to produce said output signal at said transmission rate; said interpolating means comprising: storage means for successively storing said sampled signal sequence at said predetermined sample rate to produce a sequence of stored signals at said transmission rate; interpolation means responsive to said stored signal sequence and to first and second control signals for interpolating said stored signal sequence with reference to said first and second control signals in order to produce first and second partial interpolated signals and responsive thereto said interpolated signal sequence; and said processing means comprising: detection means responsive to said interpolated signal sequence for detecting phases of said first partial interpolated signals in relation to said sampling rate to produce a sequence of phase signals which are representative of said phases; calculating means responsive to said phase signals for calculating first and second internal control signals related to said first and second partial interpolated signals, respectively; and reference timing signal generating means operatively coupled to said detection means for generating a sequence of reference timing signals with reference to the phases of said first partial interpolated signals; and delivery means coupled to said calculating means and said interpolation means for delivering said first and second internal control signals to said interpolation means as said first and second control signals, respectively.
Claim 2
Dependent Claim
313 words
A synchronization circuit responsive to an input signal carrying a transmission data signal and being received at a transmission rate for producing an output signal which is representative of reproductions of said transmission data signal, said circuit comprising: sampling means responsive to said input signal for sampling it at a predetermined sample rate to produce a sequence of sampled signals at said predetermined sample rate; interpolating means coupled to said sampling means for interpolating said sampled signal sequence to produce an interpolated signal sequence; and processing means coupled to said interpolating means for processing said interpolated signal sequence to produce said output signal at said transmission rate; said interpolating means comprising: storage means for successively storing said sampled signal sequence at said predetermined sample rate to produce a sequence of stored signals at said transmission rate; interpolation means responsive to said stored signal sequence and to first and second control signals for interpolating said stored signal sequence with reference to said first and second control signals in order to produce first and second partial interpolated signals and responsive thereto said interpolated signal sequence; and said processing means comprising: detection means responsive to said interpolated signal sequence for detecting phases of said first partial interpolated signals in relation to said sampling rate to produce a sequence of phase signals which are representative of said phases; calculating means responsive to said phase signals for calculating first and second internal control signals related to said first and second partial interpolated signals, respectively; and reference timing signal generating means operatively coupled to said detection means for generating a sequence of reference timing signals with reference to the phases of said first partial interpolated signals; and delivery means coupled to said calculating means and said interpolation means for delivering said first and second internal control signals to said interpolation means as said first and second control signals, respectively.
Claim 3
Dependent Claim
199 words
A synchronization circuit responsive to an input signal carrying a transmission data signal and being received at a transmission rate for producing an output signal which is representative of reproductions of said transmission data signal, said circuit comprising: sampling means responsive to said input signal for sampling it at a predetermined sample rate to produce a sequence of sampled signals at said predetermined sample rate, each of said sampled signals having a level represented by zero through (M-1) bits; interpolating means coupled to said sampling means for interpolating said sampled signal sequence to produce an interpolated signal sequence; and precessing means coupled to said interpolating means for processing said interpolated signal sequence to produce said output signal at said transmission rate; said interpolating means comprising: separating means responsive to said sampled signal sequence for separating each of said sampled signals into said zero through (M-1) bits, in parallel; zero through (M-1) elementary interpolation filters, there being M number filters for individually and successively interpolating said zero through (M-1) bits into zero through (M-1) fragmentary interpolated signals, respectively; and combining means coupled to said elementary interpolation filters for combining said zero through (M-1) fragmentary interpolated signals into said interpolated signals.
Claim 4
Dependent Claim
199 words
A synchronization circuit responsive to an input signal carrying a transmission data signal and being received at a transmission rate for producing an output signal which is representative of reproductions of said transmission data signal, said circuit comprising: sampling means responsive to said input signal for sampling it at a predetermined sample rate to produce a sequence of sampled signals at said predetermined sample rate, each of said sampled signals having a level represented by zero through (M-1) bits; interpolating means coupled to said sampling means for interpolating said sampled signal sequence to produce an interpolated signal sequence; and precessing means coupled to said interpolating means for processing said interpolated signal sequence to produce said output signal at said transmission rate; said interpolating means comprising: separating means responsive to said sampled signal sequence for separating each of said sampled signals into said zero through (M-1) bits, in parallel; zero through (M-1) elementary interpolation filters, there being M number filters for individually and successively interpolating said zero through (M-1) bits into zero through (M-1) fragmentary interpolated signals, respectively; and combining means coupled to said elementary interpolation filters for combining said zero through (M-1) fragmentary interpolated signals into said interpolated signals.
Claim 5
Dependent Claim
257 words
A synchronization circuit responsive to an input signal carrying a transmission data signal and being sent at a transmission rate for producing an output signal which is representative of reproductions of said transmission data signal, said circuit comprising: sampling means responsive to said input signal for sampling it at a predetermined sample rate to produce a sequence of sampled signals at said predetermined sample rate, each of said sampled signals having a level represented by zero through (M-1) bits; interpolating means coupled to said sampling means for interpolating said sampled signal sequence to produce an interpolated signal sequence; and processing means coupled to said interpolating means for processing said interpolated signal sequence to produce said output signal at said transmission rate; said interpolating means comprising: separating means responsive to said sampled signal sequence for separating each of said sampled signals into said zero through (M-1) bits, in parallel; zero through (M-1) elementary interpolator filters, there being M number, each of said filters being controllable by a sequence of timing control signals, said elementary interpolator filters individually and successively interpolating said zero through (M-1) bits into zero through (M-1) fragmentary interpolated signals in response to said timing signal, respectively; and combining means coupled to said elementary interpolation filters for combining said zero through (M-1) fragmentary interpolated signals into said interpolated signals; said processing means comprising: signal producing means coupled to said combining means for producing internal control signals from said interpolated signals; and timing control means responsive to said internal control signals for producing said timing control signals.
Claim 6
Dependent Claim
257 words
A synchronization circuit responsive to an input signal carrying a transmission data signal and being sent at a transmission rate for producing an output signal which is representative of reproductions of said transmission data signal, said circuit comprising: sampling means responsive to said input signal for sampling it at a predetermined sample rate to produce a sequence of sampled signals at said predetermined sample rate, each of said sampled signals having a level represented by zero through (M-1) bits; interpolating means coupled to said sampling means for interpolating said sampled signal sequence to produce an interpolated signal sequence; and processing means coupled to said interpolating means for processing said interpolated signal sequence to produce said output signal at said transmission rate; said interpolating means comprising: separating means responsive to said sampled signal sequence for separating each of said sampled signals into said zero through (M-1) bits, in parallel; zero through (M-1) elementary interpolator filters, there being M number, each of said filters being controllable by a sequence of timing control signals, said elementary interpolator filters individually and successively interpolating said zero through (M-1) bits into zero through (M-1) fragmentary interpolated signals in response to said timing signal, respectively; and combining means coupled to said elementary interpolation filters for combining said zero through (M-1) fragmentary interpolated signals into said interpolated signals; said processing means comprising: signal producing means coupled to said combining means for producing internal control signals from said interpolated signals; and timing control means responsive to said internal control signals for producing said timing control signals.
Claim 7
Dependent Claim
24 words
A synchronization circuit as claimed in anyone of the claims 1, 2, 3 wherein said predetermined sample rate is different from said transmission rate.
Claim 8
Dependent Claim
208 words
A synchronization circuit as claimed in anyone of the claims 1, 2, 3, said transmission data signal being produced at a transmission period determined by said transmission rate, wherein said interpolated signal sequence is divisible into first partial interpolated signals produced at said transmission rate and second partial interpolated signals which are produced at said transmission rate and delayed relative to said first partial interpolated signals by a common duration which is equal to a half of said transmission period; said processing means comprising: timing signal producing means controllable by a local input signal for producing first and second timing signals for said first and second partial interpolated signals, respectively; subsampling means coupled to said timing signal producing means and responsive to said interpolated signal sequence for subsampling said interpolated signal sequence by said first and second timing signals to produce said first and second partial interpolated signals, respectively; local processing means coupled to said subsampling means for processing said first and second partial interpolated signals to produce said output signal and an internal control signal which is dependent on said output signal and said second partial interpolated signals; and means for delivering said internal control signal to said timing signal producing means as said local input signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-09-07 | 1991-03-09 | 1991-09-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-09-07 | 1995-03-09 | 1995-09-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-09-07 | 1999-03-09 | 1999-09-08 | $7700.00 | Window Closed / Lapsed |