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US4692886A
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Digital pattern generator
Assignee: Tektronix Japan Corp
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Filing: 1985-01-24
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Granted: 1987-09-08
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Expires: 2005-01-24
Abstract
Abstract A digital pattern generator generates various kinds of digital pattern signals. A first memory stores an execution signal, an area control signal and a digital pattern. A program counter generates a first address signal in accordance with the execution signal read from the first memory and a first clock signal, and the first memory is addressed by the first address signal. Thus, the pattern generator operates as a microprogram type generator. A second memory includes a plurality of memory areas each storing a digital pattern, and a capacity of each the memory area corresponds to that of the first memory. When the second memory is addressed by a second address signal from an address counter, the pattern generator operates as a sequential type generator. When the memory area of the second memory is selected by the area control signal read from the first memory and the selected memory area is addressed by the first address signal, the second memory acts as an auxiliary memory of the first memory.
Inventors
- 👤 Yasuhiko Miki
- 👤 Kentaro Takita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:06
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/02; G06F1/03
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
148 words
A digital pattern generator comprising: a first memory for storing an execution control signal, an area control signal and a digital pattern; a clock generator for generating a clock signal; a program counter for generating a first address signal in accordance with said clock signal from said clock generator and said execution control signal from said first memory, said first address signal addressing said first memory; an address counter for generating a second address signal by counting said clock signal from said clock generator; and a second memory having a plurality of memory areas each storing a digital pattern, one of said memory areas being selected in accordance with said area control signal from said first memory, and the selected memory area being addressed by said second address signal from said address counter; whereby first and second digital patterns are derived from said first and second memories respectively.
Claim 2
Dependent Claim
148 words
A digital pattern generator comprising: a first memory for storing an execution control signal, an area control signal and a digital pattern; a clock generator for generating a clock signal; a program counter for generating a first address signal in accordance with said clock signal from said clock generator and said execution control signal from said first memory, said first address signal addressing said first memory; an address counter for generating a second address signal by counting said clock signal from said clock generator; and a second memory having a plurality of memory areas each storing a digital pattern, one of said memory areas being selected in accordance with said area control signal from said first memory, and the selected memory area being addressed by said second address signal from said address counter; whereby first and second digital patterns are derived from said first and second memories respectively.
Claim 3
Dependent Claim
36 words
A digital pattern generator according to claim 1 further including an area control circuit for selecting one of said memory areas of said second memory in response to said area control signal from said first memory.
Claim 4
Dependent Claim
42 words
A digital pattern generator according to claim 2, wherein said area control circuit is a counter for counting said area control signal from said first memory, the counted output from said counter selecting one of said memory areas of said second memory.
Claim 5
Dependent Claim
41 words
A digital pattern generator according to claim 2, wherein said area control circuit is a register for storing said area control signal from said first memory, the stored area control signal selecting one of said memory areas of said second memory.
Claim 6
Dependent Claim
128 words
A digital pattern generator comprising: a first memory for storing an execution control signal, an area control signal and a digital pattern; a clock generator for generating a clock signal; a program counter for generating an address signal in accordance with said clock signal from said clock generator and said execution control signal from said first memory, said first address signal addressing said first memory; and a second memory having a plurality of memory areas each storing a digital pattern, one of said memory areas being selected in accordance with said area control signal from said first memory, and the selected memory area being addressed by said address signal from said program counter; whereby first and second digital patterns are derived from said first and second memories respectively.
Claim 7
Dependent Claim
128 words
A digital pattern generator comprising: a first memory for storing an execution control signal, an area control signal and a digital pattern; a clock generator for generating a clock signal; a program counter for generating an address signal in accordance with said clock signal from said clock generator and said execution control signal from said first memory, said first address signal addressing said first memory; and a second memory having a plurality of memory areas each storing a digital pattern, one of said memory areas being selected in accordance with said area control signal from said first memory, and the selected memory area being addressed by said address signal from said program counter; whereby first and second digital patterns are derived from said first and second memories respectively.
Claim 8
Dependent Claim
36 words
A digital pattern generator according to claim 5 further including an area control circuit for selecting one of said memory areas of said second memory in response to said area control signal from said first memory.
Claim 9
Dependent Claim
42 words
A digital pattern generator according to claim 6, wherein said area control circuit is a counter for counting said area control signal from said first memory, the counted output from said counter selecting one of said memory areas of said second memory.
Claim 10
Dependent Claim
41 words
A digital pattern generator according to claim 6, wherein said area control circuit is a register for storing said area control signal from said first memory, the stored area control signal selecting one of said memory areas of said second memory.
Claim 11
Dependent Claim
156 words
A digital pattern generator, comprising: a first memory for storing an execution control signal an area control signal and a digital pattern; a clock generator for generating a clock signal; a program counter for generating a first address signal in accordance with said clock signal from said clock generator and said execution control signal from said first memory, said first address signal addressing said first memory; an address counter for generating a second address signal by counting said clock signal from said clock generator; selection means for selecting one of said first address signal from said program counter and said second address signal from said address counter; and a second memory having a plurality of memory areas each storing a digital pattern, one of said memory areas being selected in accordance with said area control signal from said first memory, and the selected memory area being addressed by the address signal selected by said selection means.
Claim 12
Dependent Claim
156 words
A digital pattern generator, comprising: a first memory for storing an execution control signal an area control signal and a digital pattern; a clock generator for generating a clock signal; a program counter for generating a first address signal in accordance with said clock signal from said clock generator and said execution control signal from said first memory, said first address signal addressing said first memory; an address counter for generating a second address signal by counting said clock signal from said clock generator; selection means for selecting one of said first address signal from said program counter and said second address signal from said address counter; and a second memory having a plurality of memory areas each storing a digital pattern, one of said memory areas being selected in accordance with said area control signal from said first memory, and the selected memory area being addressed by the address signal selected by said selection means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-09-07 | 1991-03-09 | 1991-09-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-09-07 | 1995-03-09 | 1995-09-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-09-07 | 1999-03-09 | 1999-09-08 | $7700.00 | Window Closed / Lapsed |