Patent US4691126A successfully refreshed from Google Patents.
US4691126A
Expired / Lapsed
US
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Redundant synchronous clock system
Assignee: Unisys Corp
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Filing: 1985-08-29
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Granted: 1987-09-01
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Expires: 2005-08-29
Abstract
Abstract A synchronous clock circuit is provided on each module of an electronic digital system formed of a plurality of modules. Each clock circuit has two control pins which are used by control logic to determine whether or not the clock on a particular module is disabled, is operating as the master clock for the system, or is providing a backup function for the master clock. The common clock line is supplied through a buffer to the components on the module which require clocking. Logic circuitry on the backup clock mode insures the backup clock is in a ready condition in case there should be either failure of the master clock oscillator or if the master clock module is removed from the unit. All of the clock circuits of the different modules may be constructed in an identical manner, with the control of the function of the circuitry being provided simply by control of the logic level on the two terminals. A clock detecting time-out circuit is provided on each of the modules, which has a timing period which is slightly longer than the clock period. If the master clock fails to produce a clock pulse at the time that it should, the clock detect timing circuit, which is coupled to the buffer of the backup module, will sense that a failure has occurred and will control the turn-on of the clock circuit for the backup module.
Inventors
- 👤 Katherine A. Splett
- 👤 James A. Howe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 08:35
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/1604; G06F1/00; G06F1/04; G06F11/20
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
232 words
A redundant clock system for an electronic digital logic system that has a common clock bus and is implemented with a plurality of digital clock circuits located on separate modules of said digital logic system comprising at least first and second modules, first and second alternately activatable clock generating means located on said first and second modules, coupled to supply a train of clock pulses to said clock bus from the activated one of said first and second clock generating means, wherein said first clock generating means is initially activated and said second clock generating means is initially deactivated, timing means located on said second module coupled to monitor the clock pulse pulses supplied on said clock bus by said first clock generating means to control a time-out period upon the occurrence of each clock pulse on said clock bus supplied by said first clock generating means and to supply a time-out signal when the interval after a monitored clock pulse exceeds a predetermined time interval and control means coupled to said timing means and constructed to maintain said first clock generator means in an activated state and said second clock generator means in a deactivated state until such time that said timing means has transmitted a time-out signal and to then switch said second clock generator means to an activated state and said first clock generating means to a deactivated state.
Claim 2
Dependent Claim
232 words
A redundant clock system for an electronic digital logic system that has a common clock bus and is implemented with a plurality of digital clock circuits located on separate modules of said digital logic system comprising at least first and second modules, first and second alternately activatable clock generating means located on said first and second modules, coupled to supply a train of clock pulses to said clock bus from the activated one of said first and second clock generating means, wherein said first clock generating means is initially activated and said second clock generating means is initially deactivated, timing means located on said second module coupled to monitor the clock pulse pulses supplied on said clock bus by said first clock generating means to control a time-out period upon the occurrence of each clock pulse on said clock bus supplied by said first clock generating means and to supply a time-out signal when the interval after a monitored clock pulse exceeds a predetermined time interval and control means coupled to said timing means and constructed to maintain said first clock generator means in an activated state and said second clock generator means in a deactivated state until such time that said timing means has transmitted a time-out signal and to then switch said second clock generator means to an activated state and said first clock generating means to a deactivated state.
Claim 3
Dependent Claim
54 words
A redundant clock system as claimed in claim 1 wherein said clock circuits are identical on all modules of said digital logic system and said control means is coupled to deactivate said clock generator means on said first module when said clock generator means on said second module is switched to an activated state.
Claim 4
Dependent Claim
52 words
A redundant clock system as claimed in claim 1 wherein said clock circuits are identical on all modules of the system and said clock generator means on said second module is switched to an activated state when the module containing said first clock generator means is removed from said digital logic system.
Claim 5
Dependent Claim
93 words
A redundant clock system as claimed in claim 1 wherein said clock circuits are identical on all modules of the system and said control means on all of said modules are coupled to first and second control terminals and one of said control terminals on said first module is interconnected with one of said control terminals on said second module and the other said control terminals of said first module is at a first logic level while the other of said control terminals of said second module is at a second logic level.
Claim 6
Dependent Claim
53 words
A redundant clock system as claimed in claim 1 wherein said clock circuits are identical on all modules of the system, and each of said modules each comprises a clock terminal which is coupled to said clock bus and to said clock generator means and said control means on each of said modules.
Claim 7
Dependent Claim
38 words
A redundant clock system as claimed in claim 1 wherein said clock circuits are identical on all modules of the system and all of said modules have a common reset terminal which is coupled to said control means.
Claim 8
Dependent Claim
49 words
A redundant clock system as claimed in claim 4 wherein said clock circuits are identical on all modules of the system and said modules each comprise a clock terminal which is coupled to said clock bus and to said clock generator means and said control means on said module.
Claim 9
Dependent Claim
38 words
A redundant clock system as claimed in claim 7 wherein said clock circuits are identical on all modules of the system and all of said modules have a common reset terminal which is coupled to said control means.
Claim 10
Dependent Claim
54 words
A redundant clock system as claimed in claim 8 wherein said clock circuits are identical on all modules of said digital logic system and said control means is coupled to deactivate said clock generator means on said first module when said clock generator means on said second module is switched to an activated state.
Claim 11
Dependent Claim
52 words
A redundant clock system is claimed in claim 8 wherein said clock circuits are identical on all modules of the system and said clock generator means on said second module is switched to an activated state when the module containing said first clock generator means is removed from said digital logic system.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-08-31 | 1991-03-02 | 1991-09-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-08-31 | 1995-03-02 | 1995-09-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-08-31 | 1999-03-02 | 1999-09-01 | $7700.00 | Window Closed / Lapsed |